206 lines
6.2 KiB
Coq
206 lines
6.2 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE AC 97 Controller ////
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//// Serial Output Controller ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: ac97_soc.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
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//
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// $Date: 2002/09/19 06:30:56 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: ac97_soc.v,v $
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// Revision 1.3 2002/09/19 06:30:56 rudi
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// Fixed a bug reported by Igor. Apparently this bug only shows up when
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// the WB clock is very low (2x bit_clk). Updated Copyright header.
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//
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// Revision 1.2 2002/03/05 04:44:05 rudi
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//
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Many minor synthesis cleanup items ...
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//
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
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// Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_soc(clk, wclk, rst,
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ps_ce, resume, suspended,
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sync, out_le, in_valid, ld, valid
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);
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input clk, wclk, rst;
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input ps_ce;
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input resume;
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output suspended;
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output sync;
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output [5:0] out_le;
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output [2:0] in_valid;
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output ld;
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output valid;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg [7:0] cnt;
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reg sync_beat;
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reg sync_resume;
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reg [5:0] out_le;
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reg ld;
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reg valid;
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reg [2:0] in_valid;
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reg bit_clk_r;
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reg bit_clk_r1;
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reg bit_clk_e;
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reg suspended;
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wire to;
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reg [5:0] to_cnt;
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reg [3:0] res_cnt;
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wire resume_done;
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assign sync = sync_beat | sync_resume;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(posedge clk or negedge rst)
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if(!rst) cnt <= #1 8'hff;
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else
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if(suspended) cnt <= #1 8'hff;
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else cnt <= #1 cnt + 8'h1;
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always @(posedge clk)
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ld <= #1 (cnt == 8'h00);
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always @(posedge clk)
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sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
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always @(posedge clk)
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valid <= #1 (cnt > 8'h39);
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always @(posedge clk)
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out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
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always @(posedge clk)
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out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
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always @(posedge clk)
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out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
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always @(posedge clk)
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out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
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always @(posedge clk)
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out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
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always @(posedge clk)
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out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
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always @(posedge clk)
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in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
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always @(posedge clk)
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in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
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always @(posedge clk)
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in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
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////////////////////////////////////////////////////////////////////
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//
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// Suspend Detect
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//
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always @(posedge wclk)
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bit_clk_r <= #1 clk;
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always @(posedge wclk)
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bit_clk_r1 <= #1 bit_clk_r;
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always @(posedge wclk)
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bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
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always @(posedge wclk)
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suspended <= #1 to;
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assign to = (to_cnt == `AC97_SUSP_DET);
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always @(posedge wclk or negedge rst)
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if(!rst) to_cnt <= #1 6'h0;
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else
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if(bit_clk_e) to_cnt <= #1 6'h0;
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else
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if(!to) to_cnt <= #1 to_cnt + 6'h1;
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////////////////////////////////////////////////////////////////////
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//
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// Resume Signaling
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//
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always @(posedge wclk or negedge rst)
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if(!rst) sync_resume <= #1 1'b0;
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else
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if(resume_done) sync_resume <= #1 1'b0;
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else
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if(suspended & resume) sync_resume <= #1 1'b1;
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assign resume_done = (res_cnt == `AC97_RES_SIG);
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always @(posedge wclk)
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if(!sync_resume) res_cnt <= #1 4'h0;
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else
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if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
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endmodule
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