OpenFPGA/yosys/examples/basys3/README

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A simple example design, based on the Digilent BASYS3 board
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This example uses Yosys for synthesis and Xilinx Vivado
for place&route and bit-stream creation.
Running Yosys:
yosys run_yosys.ys
Running Vivado:
vivado -nolog -nojournal -mode batch -source run_vivado.tcl
Programming board:
vivado -nolog -nojournal -mode batch -source run_prog.tcl
All of the above:
bash run.sh