OpenFPGA

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tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script		2018-11-30 21:14:43 -07:00
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README	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
example.v	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
example.xdc	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run.sh	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run_prog.tcl	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run_vivado.tcl	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run_yosys.ys	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00

README

A simple example design, based on the Digilent BASYS3 board
===========================================================

This example uses Yosys for synthesis and Xilinx Vivado
for place&route and bit-stream creation.

Running Yosys:
  yosys run_yosys.ys

Running Vivado:
  vivado -nolog -nojournal -mode batch -source run_vivado.tcl

Programming board:
  vivado -nolog -nojournal -mode batch -source run_prog.tcl

All of the above:
  bash run.sh