2019-05-16 15:30:16 -05:00
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#!/bin/bash
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2019-05-15 16:57:05 -05:00
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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2019-05-16 15:30:16 -05:00
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benchmark="test_modes"
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2019-06-14 12:44:44 -05:00
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OpenFPGA_path="OPENFPGAPATHKEYWORD"
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2019-05-16 15:30:16 -05:00
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$PWD"
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2019-06-06 12:47:51 -05:00
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tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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2019-05-15 16:57:05 -05:00
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# VPR critical inputs
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2019-08-14 10:10:13 -05:00
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template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
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2019-08-14 11:10:27 -05:00
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
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2019-06-06 12:47:51 -05:00
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blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
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act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
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2019-07-16 08:04:45 -05:00
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vpr_route_chan_width="300"
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2019-06-11 15:28:58 -05:00
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fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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2019-06-14 12:44:44 -05:00
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ff_path="$vpr_path/VerilogNetlists/ff.v"
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new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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ff_keyword="GENERATED_DIR_KEYWORD"
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ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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arch_ff_keyword="FFPATHKEYWORD"
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2019-05-15 16:57:05 -05:00
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# Remove previous designs
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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2019-07-16 14:13:30 -05:00
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mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated
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2019-06-11 15:28:58 -05:00
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cd $fpga_flow_scripts
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2019-06-14 12:44:44 -05:00
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perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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2019-06-11 15:28:58 -05:00
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cd -
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2019-05-15 16:57:05 -05:00
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# Run VPR
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2019-07-17 08:54:23 -05:00
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echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
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2019-07-16 14:13:30 -05:00
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
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2019-05-15 16:57:05 -05:00
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2019-06-14 12:44:44 -05:00
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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cd -
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