312 lines
9.0 KiB
Coq
312 lines
9.0 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Discrete Cosine Transform, Parallel implementation ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: dct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
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//
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// $Date: 2002-10-31 12:50:03 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:06:59 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module dct(
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clk,
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ena,
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rst,
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dstrb,
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din,
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dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
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dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
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dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
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dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
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dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
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dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
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dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
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dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77,
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douten
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);
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//
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// parameters
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//
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// Worst case errors (Din = 64* -128) remain in decimal bit
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// when using 13bit coefficients
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//
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// For ultra-high
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parameter coef_width = 11;
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parameter di_width = 8;
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parameter do_width = 12;
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//
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// inputs & outputs
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//
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input clk;
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input ena;
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input rst; // active low asynchronous reset
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input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
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input [di_width:1] din;
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output [do_width:1]
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dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
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dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
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dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
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dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
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dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
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dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
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dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
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dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77;
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output douten; // data-out enable
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reg douten;
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//
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// variables
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//
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reg go, dgo, ddgo, ddcnt, dddcnt;
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reg [di_width:1] ddin;
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//
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// module body
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//
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// generate sample counter
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reg [5:0] sample_cnt;
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wire dcnt = &sample_cnt;
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always @(posedge clk or negedge rst)
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if (~rst)
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sample_cnt <= #1 6'h0;
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else if (ena)
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if(dstrb)
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sample_cnt <= #1 6'h0;
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else if(~dcnt)
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sample_cnt <= #1 sample_cnt + 6'h1;
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// internal signals
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always @(posedge clk or negedge rst)
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if (~rst)
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begin
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go <= #1 1'b0;
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dgo <= #1 1'b0;
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ddgo <= #1 1'b0;
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ddin <= #1 0;
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douten <= #1 1'b0;
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ddcnt <= #1 1'b1;
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dddcnt <= #1 1'b1;
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end
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else if (ena)
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begin
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go <= #1 dstrb;
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dgo <= #1 go;
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ddgo <= #1 dgo;
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ddin <= #1 din;
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ddcnt <= #1 dcnt;
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dddcnt <= #1 ddcnt;
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douten <= #1 ddcnt & ~dddcnt;
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end
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// Hookup DCT units
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// V = 0
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dctub #(coef_width, di_width, 3'h0)
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dct_block_0 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_00), // (U,V) = (0,0)
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.dout1(dout_01), // (U,V) = (0,1)
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.dout2(dout_02), // (U,V) = (0,2)
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.dout3(dout_03), // (U,V) = (0,3)
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.dout4(dout_04), // (U,V) = (0,4)
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.dout5(dout_05), // (U,V) = (0,5)
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.dout6(dout_06), // (U,V) = (0,6)
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.dout7(dout_07) // (U,V) = (0,7)
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);
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// V = 1
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dctub #(coef_width, di_width, 3'h1)
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dct_block_1 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_10), // (U,V) = (1,0)
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.dout1(dout_11), // (U,V) = (1,1)
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.dout2(dout_12), // (U,V) = (1,2)
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.dout3(dout_13), // (U,V) = (1,3)
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.dout4(dout_14), // (U,V) = (1,4)
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.dout5(dout_15), // (U,V) = (1,5)
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.dout6(dout_16), // (U,V) = (1,6)
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.dout7(dout_17) // (U,V) = (1,7)
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);
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// V = 2
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dctub #(coef_width, di_width, 3'h2)
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dct_block_2 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_20), // (U,V) = (2,0)
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.dout1(dout_21), // (U,V) = (2,1)
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.dout2(dout_22), // (U,V) = (2,2)
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.dout3(dout_23), // (U,V) = (2,3)
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.dout4(dout_24), // (U,V) = (2,4)
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.dout5(dout_25), // (U,V) = (2,5)
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.dout6(dout_26), // (U,V) = (2,6)
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.dout7(dout_27) // (U,V) = (2,7)
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);
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// V = 3
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dctub #(coef_width, di_width, 3'h3)
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dct_block_3 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_30), // (U,V) = (3,0)
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.dout1(dout_31), // (U,V) = (3,1)
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.dout2(dout_32), // (U,V) = (3,2)
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.dout3(dout_33), // (U,V) = (3,3)
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.dout4(dout_34), // (U,V) = (3,4)
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.dout5(dout_35), // (U,V) = (3,5)
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.dout6(dout_36), // (U,V) = (3,6)
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.dout7(dout_37) // (U,V) = (3,7)
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);
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// V = 4
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dctub #(coef_width, di_width, 3'h4)
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dct_block_4 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_40), // (U,V) = (4,0)
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.dout1(dout_41), // (U,V) = (4,1)
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.dout2(dout_42), // (U,V) = (4,2)
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.dout3(dout_43), // (U,V) = (4,3)
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.dout4(dout_44), // (U,V) = (4,4)
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.dout5(dout_45), // (U,V) = (4,5)
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.dout6(dout_46), // (U,V) = (4,6)
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.dout7(dout_47) // (U,V) = (4,7)
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);
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// V = 5
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dctub #(coef_width, di_width, 3'h5)
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dct_block_5 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_50), // (U,V) = (5,0)
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.dout1(dout_51), // (U,V) = (5,1)
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.dout2(dout_52), // (U,V) = (5,2)
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.dout3(dout_53), // (U,V) = (5,3)
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.dout4(dout_54), // (U,V) = (5,4)
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.dout5(dout_55), // (U,V) = (5,5)
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.dout6(dout_56), // (U,V) = (5,6)
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.dout7(dout_57) // (U,V) = (5,7)
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);
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// V = 6
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dctub #(coef_width, di_width, 3'h6)
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dct_block_6 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_60), // (U,V) = (6,0)
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.dout1(dout_61), // (U,V) = (6,1)
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.dout2(dout_62), // (U,V) = (6,2)
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.dout3(dout_63), // (U,V) = (6,3)
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.dout4(dout_64), // (U,V) = (6,4)
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.dout5(dout_65), // (U,V) = (6,5)
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.dout6(dout_66), // (U,V) = (6,6)
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.dout7(dout_67) // (U,V) = (6,7)
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);
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// V = 7
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dctub #(coef_width, di_width, 3'h7)
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dct_block_7 (
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.clk(clk),
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.ena(ena),
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.ddgo(ddgo),
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.x(sample_cnt[2:0]),
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.y(sample_cnt[5:3]),
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.ddin(ddin),
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.dout0(dout_70), // (U,V) = (7,0)
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.dout1(dout_71), // (U,V) = (7,1)
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.dout2(dout_72), // (U,V) = (7,2)
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.dout3(dout_73), // (U,V) = (7,3)
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.dout4(dout_74), // (U,V) = (7,4)
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.dout5(dout_75), // (U,V) = (7,5)
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.dout6(dout_76), // (U,V) = (7,6)
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.dout7(dout_77) // (U,V) = (7,7)
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);
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endmodule
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