OpenFPGA/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v

//---------------------------------------
// 1-bit adder 
//---------------------------------------
module adder(
	input cin,
	input a,
	input b,
	output cout,
	output sumout );


	assign sumout = a ^ b ^ cin;
	assign cout = (a & b) | ((a | b) & cin);

endmodule