443 lines
11 KiB
Coq
443 lines
11 KiB
Coq
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//
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// TV80 8-Bit Microprocessor Core
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// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80_alu (/*AUTOARG*/
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// Outputs
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Q, F_Out,
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// Inputs
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Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
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);
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parameter Mode = 0;
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parameter Flag_C = 0;
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parameter Flag_N = 1;
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parameter Flag_P = 2;
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parameter Flag_X = 3;
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parameter Flag_H = 4;
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parameter Flag_Y = 5;
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parameter Flag_Z = 6;
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parameter Flag_S = 7;
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input Arith16;
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input Z16;
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input [3:0] ALU_Op ;
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input [5:0] IR;
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input [1:0] ISet;
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input [7:0] BusA;
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input [7:0] BusB;
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input [7:0] F_In;
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output [7:0] Q;
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output [7:0] F_Out;
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reg [7:0] Q;
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reg [7:0] F_Out;
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function [4:0] AddSub4;
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input [3:0] A;
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input [3:0] B;
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input Sub;
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input Carry_In;
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begin
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AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
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end
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endfunction // AddSub4
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function [3:0] AddSub3;
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input [2:0] A;
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input [2:0] B;
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input Sub;
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input Carry_In;
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begin
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AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
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end
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endfunction // AddSub4
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function [1:0] AddSub1;
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input A;
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input B;
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input Sub;
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input Carry_In;
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begin
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AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
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end
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endfunction // AddSub4
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// AddSub variables (temporary signals)
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reg UseCarry;
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reg Carry7_v;
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reg OverFlow_v;
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reg HalfCarry_v;
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reg Carry_v;
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reg [7:0] Q_v;
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reg [7:0] BitMask;
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always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
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begin
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case (IR[5:3])
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3'b000 : BitMask = 8'b00000001;
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3'b001 : BitMask = 8'b00000010;
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3'b010 : BitMask = 8'b00000100;
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3'b011 : BitMask = 8'b00001000;
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3'b100 : BitMask = 8'b00010000;
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3'b101 : BitMask = 8'b00100000;
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3'b110 : BitMask = 8'b01000000;
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default: BitMask = 8'b10000000;
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endcase // case(IR[5:3])
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UseCarry = ~ ALU_Op[2] && ALU_Op[0];
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{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
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{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
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{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
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OverFlow_v = Carry_v ^ Carry7_v;
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end // always @ *
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reg [7:0] Q_t;
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reg [8:0] DAA_Q;
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always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
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or Carry_v or F_In or HalfCarry_v or IR or ISet
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or OverFlow_v or Q_v or Z16)
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begin
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Q_t = 8'hxx;
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DAA_Q = {9{1'bx}};
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F_Out = F_In;
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case (ALU_Op)
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4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
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begin
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F_Out[Flag_N] = 1'b0;
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F_Out[Flag_C] = 1'b0;
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case (ALU_Op[2:0])
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3'b000, 3'b001 : // ADD, ADC
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begin
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Q_t = Q_v;
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F_Out[Flag_C] = Carry_v;
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F_Out[Flag_H] = HalfCarry_v;
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F_Out[Flag_P] = OverFlow_v;
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end
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3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
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begin
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Q_t = Q_v;
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F_Out[Flag_N] = 1'b1;
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F_Out[Flag_C] = ~ Carry_v;
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F_Out[Flag_H] = ~ HalfCarry_v;
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F_Out[Flag_P] = OverFlow_v;
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end
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3'b100 : // AND
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begin
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Q_t[7:0] = BusA & BusB;
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F_Out[Flag_H] = 1'b1;
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end
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3'b101 : // XOR
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begin
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Q_t[7:0] = BusA ^ BusB;
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F_Out[Flag_H] = 1'b0;
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end
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default : // OR 3'b110
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begin
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Q_t[7:0] = BusA | BusB;
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F_Out[Flag_H] = 1'b0;
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end
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endcase // case(ALU_OP[2:0])
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if (ALU_Op[2:0] == 3'b111 )
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begin // CP
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F_Out[Flag_X] = BusB[3];
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F_Out[Flag_Y] = BusB[5];
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end
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else
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begin
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F_Out[Flag_X] = Q_t[3];
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F_Out[Flag_Y] = Q_t[5];
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end
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if (Q_t[7:0] == 8'b00000000 )
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begin
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F_Out[Flag_Z] = 1'b1;
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if (Z16 == 1'b1 )
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begin
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F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
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end
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end
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else
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begin
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F_Out[Flag_Z] = 1'b0;
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end // else: !if(Q_t[7:0] == 8'b00000000 )
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F_Out[Flag_S] = Q_t[7];
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case (ALU_Op[2:0])
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3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
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;
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default :
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F_Out[Flag_P] = ~(^Q_t);
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endcase // case(ALU_Op[2:0])
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if (Arith16 == 1'b1 )
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begin
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F_Out[Flag_S] = F_In[Flag_S];
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F_Out[Flag_Z] = F_In[Flag_Z];
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F_Out[Flag_P] = F_In[Flag_P];
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end
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end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
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4'b1100 :
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begin
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// DAA
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F_Out[Flag_H] = F_In[Flag_H];
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F_Out[Flag_C] = F_In[Flag_C];
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DAA_Q[7:0] = BusA;
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DAA_Q[8] = 1'b0;
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if (F_In[Flag_N] == 1'b0 )
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begin
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// After addition
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// Alow > 9 || H == 1
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if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
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begin
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if ((DAA_Q[3:0] > 9) )
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begin
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F_Out[Flag_H] = 1'b1;
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end
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else
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begin
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F_Out[Flag_H] = 1'b0;
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end
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DAA_Q = DAA_Q + 6;
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end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
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// new Ahigh > 9 || C == 1
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if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
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begin
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DAA_Q = DAA_Q + 96; // 0x60
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end
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end
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else
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begin
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// After subtraction
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if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
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begin
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if (DAA_Q[3:0] > 5 )
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begin
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F_Out[Flag_H] = 1'b0;
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end
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DAA_Q[7:0] = DAA_Q[7:0] - 6;
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end
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if (BusA > 153 || F_In[Flag_C] == 1'b1 )
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begin
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DAA_Q = DAA_Q - 352; // 0x160
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end
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end // else: !if(F_In[Flag_N] == 1'b0 )
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F_Out[Flag_X] = DAA_Q[3];
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F_Out[Flag_Y] = DAA_Q[5];
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F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
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Q_t = DAA_Q[7:0];
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if (DAA_Q[7:0] == 8'b00000000 )
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begin
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F_Out[Flag_Z] = 1'b1;
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end
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else
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begin
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F_Out[Flag_Z] = 1'b0;
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end
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F_Out[Flag_S] = DAA_Q[7];
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F_Out[Flag_P] = ~ (^DAA_Q);
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end // case: 4'b1100
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4'b1101, 4'b1110 :
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begin
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// RLD, RRD
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Q_t[7:4] = BusA[7:4];
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if (ALU_Op[0] == 1'b1 )
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begin
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Q_t[3:0] = BusB[7:4];
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end
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else
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begin
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Q_t[3:0] = BusB[3:0];
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end
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F_Out[Flag_H] = 1'b0;
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F_Out[Flag_N] = 1'b0;
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F_Out[Flag_X] = Q_t[3];
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F_Out[Flag_Y] = Q_t[5];
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if (Q_t[7:0] == 8'b00000000 )
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begin
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F_Out[Flag_Z] = 1'b1;
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end
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else
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begin
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F_Out[Flag_Z] = 1'b0;
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end
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F_Out[Flag_S] = Q_t[7];
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F_Out[Flag_P] = ~(^Q_t);
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end // case: when 4'b1101, 4'b1110
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4'b1001 :
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begin
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// BIT
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Q_t[7:0] = BusB & BitMask;
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F_Out[Flag_S] = Q_t[7];
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if (Q_t[7:0] == 8'b00000000 )
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begin
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F_Out[Flag_Z] = 1'b1;
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F_Out[Flag_P] = 1'b1;
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end
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else
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begin
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F_Out[Flag_Z] = 1'b0;
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F_Out[Flag_P] = 1'b0;
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end
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F_Out[Flag_H] = 1'b1;
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F_Out[Flag_N] = 1'b0;
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F_Out[Flag_X] = 1'b0;
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F_Out[Flag_Y] = 1'b0;
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if (IR[2:0] != 3'b110 )
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begin
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F_Out[Flag_X] = BusB[3];
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F_Out[Flag_Y] = BusB[5];
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end
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end // case: when 4'b1001
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4'b1010 :
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// SET
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Q_t[7:0] = BusB | BitMask;
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4'b1011 :
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// RES
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Q_t[7:0] = BusB & ~ BitMask;
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4'b1000 :
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begin
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// ROT
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case (IR[5:3])
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3'b000 : // RLC
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begin
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Q_t[7:1] = BusA[6:0];
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Q_t[0] = BusA[7];
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F_Out[Flag_C] = BusA[7];
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end
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3'b010 : // RL
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begin
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Q_t[7:1] = BusA[6:0];
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Q_t[0] = F_In[Flag_C];
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F_Out[Flag_C] = BusA[7];
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end
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3'b001 : // RRC
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begin
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Q_t[6:0] = BusA[7:1];
|
||
|
|
Q_t[7] = BusA[0];
|
||
|
|
F_Out[Flag_C] = BusA[0];
|
||
|
|
end
|
||
|
|
|
||
|
|
3'b011 : // RR
|
||
|
|
begin
|
||
|
|
Q_t[6:0] = BusA[7:1];
|
||
|
|
Q_t[7] = F_In[Flag_C];
|
||
|
|
F_Out[Flag_C] = BusA[0];
|
||
|
|
end
|
||
|
|
|
||
|
|
3'b100 : // SLA
|
||
|
|
begin
|
||
|
|
Q_t[7:1] = BusA[6:0];
|
||
|
|
Q_t[0] = 1'b0;
|
||
|
|
F_Out[Flag_C] = BusA[7];
|
||
|
|
end
|
||
|
|
|
||
|
|
3'b110 : // SLL (Undocumented) / SWAP
|
||
|
|
begin
|
||
|
|
if (Mode == 3 )
|
||
|
|
begin
|
||
|
|
Q_t[7:4] = BusA[3:0];
|
||
|
|
Q_t[3:0] = BusA[7:4];
|
||
|
|
F_Out[Flag_C] = 1'b0;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
Q_t[7:1] = BusA[6:0];
|
||
|
|
Q_t[0] = 1'b1;
|
||
|
|
F_Out[Flag_C] = BusA[7];
|
||
|
|
end // else: !if(Mode == 3 )
|
||
|
|
end // case: 3'b110
|
||
|
|
|
||
|
|
3'b101 : // SRA
|
||
|
|
begin
|
||
|
|
Q_t[6:0] = BusA[7:1];
|
||
|
|
Q_t[7] = BusA[7];
|
||
|
|
F_Out[Flag_C] = BusA[0];
|
||
|
|
end
|
||
|
|
|
||
|
|
default : // SRL
|
||
|
|
begin
|
||
|
|
Q_t[6:0] = BusA[7:1];
|
||
|
|
Q_t[7] = 1'b0;
|
||
|
|
F_Out[Flag_C] = BusA[0];
|
||
|
|
end
|
||
|
|
endcase // case(IR[5:3])
|
||
|
|
|
||
|
|
F_Out[Flag_H] = 1'b0;
|
||
|
|
F_Out[Flag_N] = 1'b0;
|
||
|
|
F_Out[Flag_X] = Q_t[3];
|
||
|
|
F_Out[Flag_Y] = Q_t[5];
|
||
|
|
F_Out[Flag_S] = Q_t[7];
|
||
|
|
if (Q_t[7:0] == 8'b00000000 )
|
||
|
|
begin
|
||
|
|
F_Out[Flag_Z] = 1'b1;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
F_Out[Flag_Z] = 1'b0;
|
||
|
|
end
|
||
|
|
F_Out[Flag_P] = ~(^Q_t);
|
||
|
|
|
||
|
|
if (ISet == 2'b00 )
|
||
|
|
begin
|
||
|
|
F_Out[Flag_P] = F_In[Flag_P];
|
||
|
|
F_Out[Flag_S] = F_In[Flag_S];
|
||
|
|
F_Out[Flag_Z] = F_In[Flag_Z];
|
||
|
|
end
|
||
|
|
end // case: 4'b1000
|
||
|
|
|
||
|
|
|
||
|
|
default :
|
||
|
|
;
|
||
|
|
|
||
|
|
endcase // case(ALU_Op)
|
||
|
|
|
||
|
|
Q = Q_t;
|
||
|
|
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||
|
|
|
||
|
|
endmodule // T80_ALU
|