202 lines
9.3 KiB
Coq
202 lines
9.3 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: pci_decoder.v ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_pci_decoder.v,v $
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module pci_pci_decoder (hit, addr_out,
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addr_in, bc_in,
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base_addr, mask_addr, tran_addr, at_en,
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mem_io_space, mem_en, io_en) ;
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// Decoding address size parameter - for FPGAs 1MegByte is recommended
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// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!
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parameter decode_len = 12 ;
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//###########################################################################################################
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// ALL COMMENTS are written as there were decode_len 20. This number and 12 (32 - 20) are assigning the
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// numbers of decoded and compared bits, etc.
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//###########################################################################################################
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/*-----------------------------------------------------------------------------------------------------------
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DECODER interface decodes input address (ADDR_IN); what means that it validates (HIT), if input address
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falls within the defined image space boundaries. Image space boundarie is defined with image base address
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register (BASE_ADDR) and address mask register (MASK_ADDR).
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Beside that, it also translates (maps) the input address to the output address (ADDR_OUT), regarding the
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translation address register (TRAN_ADDR) and the address mask register.
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-----------------------------------------------------------------------------------------------------------*/
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// output control
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output hit ;
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// output address
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output [31:0] addr_out ;
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// input address and bus command
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input [31:0] addr_in ;
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input [3:0] bc_in ;
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// input registers - 12 LSbits are not valid since the smallest possible size is 4KB !
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input [31:(32-decode_len)] base_addr ;
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input [31:(32-decode_len)] mask_addr ;
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input [31:(32-decode_len)] tran_addr ;
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// input bit[2] of the Image Control register used to enable the address translation !
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input at_en ;
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// memory or io space selection and its enable signals !
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input mem_io_space ;
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input mem_en ;
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input io_en ;
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/*-----------------------------------------------------------------------------------------------------------
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Internal signals !
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-----------------------------------------------------------------------------------------------------------*/
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// bit[31] if address mask register is IMAGE ENABLE bit (img_en)
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wire img_en ;
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// addr_in_compare are masked input address bits that are compared with masked base_addr
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wire [31:(32-decode_len)] addr_in_compare ;
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// base_addr_compare are masked base address bits that are compared with masked addr_in
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wire [31:(32-decode_len)] base_addr_compare ;
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/*-----------------------------------------------------------------------------------------------------------
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Decoding the input address!
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This logic produces the loghest path in this module!
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20 MSbits of input addres are as well as base address (20 bits) masked with corrected address mask. Only
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masked bits of each vector are actually logically compared.
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Bit[31] of address mask register is used to enable the image space !
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Because of PCI bus specifications, there is also the comparison of memory/io selection (mem_io_space) and
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its appropriate enable bit (mem_en / io_en).
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-----------------------------------------------------------------------------------------------------------*/
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assign addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ;
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assign base_addr_compare = (base_addr & mask_addr) ;
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assign img_en = mask_addr[31] ;
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wire addr_hit = (addr_in_compare == base_addr_compare) ;
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wire space_hit = (!mem_io_space && mem_en && img_en) || (mem_io_space && io_en && img_en) ;
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reg bc_hit ;
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always@(bc_in or mem_io_space)
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begin // Allowed bus commands for accesses through IMAGEs to WB bus - BC_CONF_WRITE/READ are not used with address claim!!!
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case ( {bc_in[3:1], mem_io_space} )
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4'b001_1, // BC_IO_READ or BC_IO_WRITE and IO space
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4'b011_0, // BC_MEM_READ or BC_MEM_WRITE and MEM space
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4'b110_0, // BC_MEM_READ_MUL and MEM space - BC_DUAL_ADDR_CYC must NOT be allowed!
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4'b111_0: // BC_MEM_READ_LN or BC_MEM_WRITE_INVAL and MEM space
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bc_hit <= 1'b1 ;
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default:
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bc_hit <= 1'b0 ;
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endcase
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end
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wire bc_forbid = bc_in[3] && bc_in[2] && !bc_in[1] && bc_in[0] ; // BC_DUAL_ADDR_CYC must NOT be allowed!
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assign hit = (addr_hit && space_hit && bc_hit && !bc_forbid) ;
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/*-----------------------------------------------------------------------------------------------------------
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Translating the input address!
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Translation of input address is not implemented if ADDR_TRAN_IMPL is not defined
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20 MSbits of input address are masked with negated value of the corrected address mask in order to get
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address bits of the input address which won't be replaced with translation address bits.
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Translation address bits (20 bits) are masked with corrected address mask. Only masked bits of vector are
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actually valid, all others are zero.
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Boath vectors are bit-wise ORed in order to get the valid translation address with an offset of an input
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address.
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12 LSbits of an input address are assigned to 12 LSbits of an output addres.
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-----------------------------------------------------------------------------------------------------------*/
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`ifdef ADDR_TRAN_IMPL
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// if Address Translation Enable bit is set, then translation address is used othervise input address is used!
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// addr_in_combine input address bits are not replaced with translation address!
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wire [31:(32-decode_len)] addr_in_combine ;
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// tran_addr_combine are masked and combined with addr_in_combine!
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reg [31:(32-decode_len)] tran_addr_combine ;
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assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ;
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always@(at_en or tran_addr or mask_addr or addr_in)
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begin
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if (at_en)
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begin
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tran_addr_combine <= (tran_addr & mask_addr) ;
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end
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else
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begin
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tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ;
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end
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end
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assign addr_out[31:(32-decode_len)] = (addr_in_combine | tran_addr_combine) ;
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assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ;
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`else
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assign addr_out = addr_in ;
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`endif
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endmodule
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