856 lines
22 KiB
Coq
856 lines
22 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pci_io_mux.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_io_mux.v,v $
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// Revision 1.5 2003/12/19 11:11:30 mihad
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// Compact PCI Hot Swap support added.
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// New testcases added.
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// Specification updated.
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// Test application changed to support WB B3 cycles.
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//
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// Revision 1.4 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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// this module instantiates output flip flops for PCI interface and
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// some fanout downsizing logic because of heavily constrained PCI signals
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module pci_io_mux
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(
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reset_in,
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clk_in,
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frame_in,
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frame_en_in,
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frame_load_in,
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irdy_in,
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irdy_en_in,
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devsel_in,
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devsel_en_in,
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trdy_in,
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trdy_en_in,
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stop_in,
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stop_en_in,
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master_load_in,
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master_load_on_transfer_in,
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target_load_in,
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target_load_on_transfer_in,
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cbe_in,
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cbe_en_in,
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mas_ad_in,
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tar_ad_in,
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par_in,
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par_en_in,
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perr_in,
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perr_en_in,
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serr_in,
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serr_en_in,
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req_in,
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mas_ad_en_in,
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tar_ad_en_in,
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tar_ad_en_reg_in,
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ad_en_out,
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frame_en_out,
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irdy_en_out,
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devsel_en_out,
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trdy_en_out,
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stop_en_out,
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cbe_en_out,
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frame_out,
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irdy_out,
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devsel_out,
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trdy_out,
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stop_out,
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cbe_out,
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ad_out,
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ad_load_out,
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ad_en_unregistered_out,
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par_out,
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par_en_out,
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perr_out,
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perr_en_out,
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serr_out,
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serr_en_out,
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req_out,
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req_en_out,
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pci_trdy_in,
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pci_irdy_in,
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pci_frame_in,
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pci_stop_in,
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init_complete_in
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);
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input reset_in, clk_in ;
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input frame_in ;
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input frame_en_in ;
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input frame_load_in ;
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input irdy_in ;
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input irdy_en_in ;
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input devsel_in ;
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input devsel_en_in ;
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input trdy_in ;
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input trdy_en_in ;
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input stop_in ;
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input stop_en_in ;
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input master_load_in ;
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input target_load_in ;
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input [3:0] cbe_in ;
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input cbe_en_in ;
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input [31:0] mas_ad_in ;
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input [31:0] tar_ad_in ;
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input mas_ad_en_in ;
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input tar_ad_en_in ;
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input tar_ad_en_reg_in ;
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input par_in ;
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input par_en_in ;
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input perr_in ;
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input perr_en_in ;
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input serr_in ;
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input serr_en_in ;
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output frame_en_out ;
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output irdy_en_out ;
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output devsel_en_out ;
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output trdy_en_out ;
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output stop_en_out ;
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output [31:0] ad_en_out ;
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output [3:0] cbe_en_out ;
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output frame_out ;
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output irdy_out ;
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output devsel_out ;
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output trdy_out ;
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output stop_out ;
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output [3:0] cbe_out ;
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output [31:0] ad_out ;
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output ad_load_out ;
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output ad_en_unregistered_out ;
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output par_out ;
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output par_en_out ;
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output perr_out ;
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output perr_en_out ;
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output serr_out ;
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output serr_en_out ;
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input req_in ;
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output req_out ;
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output req_en_out ;
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input pci_trdy_in,
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pci_irdy_in,
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pci_frame_in,
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pci_stop_in ;
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input master_load_on_transfer_in ;
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input target_load_on_transfer_in ;
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input init_complete_in ;
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wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
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wire ad_en_ctrl_low ;
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wire ad_en_ctrl_mlow ;
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wire ad_en_ctrl_mhigh ;
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wire ad_en_ctrl_high ;
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wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
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pci_io_mux_ad_en_crit ad_en_low_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_low)
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);
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pci_io_mux_ad_en_crit ad_en_mlow_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_mlow)
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);
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pci_io_mux_ad_en_crit ad_en_mhigh_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_mhigh)
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);
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pci_io_mux_ad_en_crit ad_en_high_gen
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(
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.ad_en_in (ad_enable_internal),
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.pci_frame_in (pci_frame_in),
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.pci_trdy_in (pci_trdy_in),
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.pci_stop_in (pci_stop_in),
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.ad_en_out (ad_en_ctrl_high)
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);
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assign ad_en_unregistered_out = ad_en_ctrl_high ;
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wire load = master_load_in || target_load_in ;
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wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
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wire ad_load_ctrl_low ;
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wire ad_load_ctrl_mlow ;
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wire ad_load_ctrl_mhigh ;
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wire ad_load_ctrl_high ;
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assign ad_load_out = ad_load_ctrl_high ;
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pci_io_mux_ad_load_crit ad_load_low_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_low)
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);
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pci_io_mux_ad_load_crit ad_load_mlow_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_mlow)
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);
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pci_io_mux_ad_load_crit ad_load_mhigh_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_mhigh)
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);
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pci_io_mux_ad_load_crit ad_load_high_gen
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(
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.load_in(load),
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.load_on_transfer_in(load_on_transfer),
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.pci_irdy_in(pci_irdy_in),
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.pci_trdy_in(pci_trdy_in),
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.load_out(ad_load_ctrl_high)
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);
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pci_out_reg ad_iob0
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(
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.dat_en_in ( ad_load_ctrl_low ),
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.en_en_in ( 1'b1 ),
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.dat_in ( temp_ad[0] ) ,
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.en_in ( ad_en_ctrl_low ) ,
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.en_out ( ad_en_out[0] ),
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.dat_out ( ad_out[0] )
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);
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pci_out_reg ad_iob1
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(
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.dat_en_in ( ad_load_ctrl_low ),
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.en_en_in ( 1'b1 ),
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.dat_in ( temp_ad[1] ) ,
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.en_in ( ad_en_ctrl_low ) ,
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.en_out ( ad_en_out[1] ),
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.dat_out ( ad_out[1] )
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);
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pci_out_reg ad_iob2
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(
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.dat_en_in ( ad_load_ctrl_low ),
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.en_en_in ( 1'b1 ),
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.dat_in ( temp_ad[2] ) ,
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.en_in ( ad_en_ctrl_low ) ,
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.en_out ( ad_en_out[2] ),
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.dat_out ( ad_out[2] )
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);
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pci_out_reg ad_iob3
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(
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.dat_en_in ( ad_load_ctrl_low ),
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.en_en_in ( 1'b1 ),
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.dat_in ( temp_ad[3] ) ,
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.en_in ( ad_en_ctrl_low ) ,
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.en_out ( ad_en_out[3] ),
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.dat_out ( ad_out[3] )
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);
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pci_out_reg ad_iob4
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(
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.reset_in ( reset_in ),
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.clk_in ( clk_in) ,
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.dat_en_in ( ad_load_ctrl_low ),
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.en_en_in ( 1'b1 ),
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.dat_in ( temp_ad[4] ) ,
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.en_in ( ad_en_ctrl_low ) ,
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.en_out ( ad_en_out[4] ),
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.dat_out ( ad_out[4] )
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);
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||
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||
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pci_out_reg ad_iob5
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||
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(
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.reset_in ( reset_in ),
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||
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.clk_in ( clk_in) ,
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||
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.dat_en_in ( ad_load_ctrl_low ),
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||
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.en_en_in ( 1'b1 ),
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||
|
|
.dat_in ( temp_ad[5] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_low ) ,
|
||
|
|
.en_out ( ad_en_out[5] ),
|
||
|
|
.dat_out ( ad_out[5] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob6
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_low ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[6] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_low ) ,
|
||
|
|
.en_out ( ad_en_out[6] ),
|
||
|
|
.dat_out ( ad_out[6] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob7
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_low ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[7] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_low ) ,
|
||
|
|
.en_out ( ad_en_out[7] ),
|
||
|
|
.dat_out ( ad_out[7] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob8
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[8] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[8] ),
|
||
|
|
.dat_out ( ad_out[8] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob9
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[9] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[9] ),
|
||
|
|
.dat_out ( ad_out[9] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob10
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[10] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[10] ),
|
||
|
|
.dat_out ( ad_out[10] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob11
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[11] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[11] ),
|
||
|
|
.dat_out ( ad_out[11] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob12
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[12] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[12] ),
|
||
|
|
.dat_out ( ad_out[12] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob13
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[13] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[13] ),
|
||
|
|
.dat_out ( ad_out[13] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob14
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[14] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[14] ),
|
||
|
|
.dat_out ( ad_out[14] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob15
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mlow ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[15] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mlow ) ,
|
||
|
|
.en_out ( ad_en_out[15] ),
|
||
|
|
.dat_out ( ad_out[15] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob16
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[16] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[16] ),
|
||
|
|
.dat_out ( ad_out[16] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob17
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[17] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[17] ),
|
||
|
|
.dat_out ( ad_out[17] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob18
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[18] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[18] ),
|
||
|
|
.dat_out ( ad_out[18] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob19
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[19] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[19] ),
|
||
|
|
.dat_out ( ad_out[19] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob20
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[20] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[20] ),
|
||
|
|
.dat_out ( ad_out[20] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob21
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[21] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[21] ),
|
||
|
|
.dat_out ( ad_out[21] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob22
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[22] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[22] ),
|
||
|
|
.dat_out ( ad_out[22] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob23
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_mhigh ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[23] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_mhigh ) ,
|
||
|
|
.en_out ( ad_en_out[23] ),
|
||
|
|
.dat_out ( ad_out[23] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob24
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[24] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[24] ),
|
||
|
|
.dat_out ( ad_out[24] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob25
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[25] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[25] ),
|
||
|
|
.dat_out ( ad_out[25] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob26
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[26] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[26] ),
|
||
|
|
.dat_out ( ad_out[26] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob27
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[27] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[27] ),
|
||
|
|
.dat_out ( ad_out[27] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob28
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[28] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[28] ),
|
||
|
|
.dat_out ( ad_out[28] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob29
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[29] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[29] ),
|
||
|
|
.dat_out ( ad_out[29] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob30
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[30] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[30] ),
|
||
|
|
.dat_out ( ad_out[30] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg ad_iob31
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( ad_load_ctrl_high ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( temp_ad[31] ) ,
|
||
|
|
.en_in ( ad_en_ctrl_high ) ,
|
||
|
|
.en_out ( ad_en_out[31] ),
|
||
|
|
.dat_out ( ad_out[31] )
|
||
|
|
);
|
||
|
|
|
||
|
|
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
|
||
|
|
wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ;
|
||
|
|
|
||
|
|
pci_out_reg cbe_iob0
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( cbe_load_ctrl[0] ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( cbe_in[0] ) ,
|
||
|
|
.en_in ( cbe_en_ctrl[0] ) ,
|
||
|
|
.en_out ( cbe_en_out[0] ),
|
||
|
|
.dat_out ( cbe_out[0] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg cbe_iob1
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( cbe_load_ctrl[1] ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( cbe_in[1] ) ,
|
||
|
|
.en_in ( cbe_en_ctrl[1] ) ,
|
||
|
|
.en_out ( cbe_en_out[1] ),
|
||
|
|
.dat_out ( cbe_out[1] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg cbe_iob2
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( cbe_load_ctrl[2] ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( cbe_in[2] ) ,
|
||
|
|
.en_in ( cbe_en_ctrl[2] ) ,
|
||
|
|
.en_out ( cbe_en_out[2] ),
|
||
|
|
.dat_out ( cbe_out[2] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg cbe_iob3
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( cbe_load_ctrl[3] ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( cbe_in[3] ) ,
|
||
|
|
.en_in ( cbe_en_ctrl[3] ) ,
|
||
|
|
.en_out ( cbe_en_out[3] ),
|
||
|
|
.dat_out ( cbe_out[3] )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg frame_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( frame_load_in ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( frame_in ) ,
|
||
|
|
.en_in ( frame_en_in ) ,
|
||
|
|
.en_out ( frame_en_out ),
|
||
|
|
.dat_out ( frame_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg irdy_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( irdy_in ) ,
|
||
|
|
.en_in ( irdy_en_in ) ,
|
||
|
|
.en_out ( irdy_en_out ),
|
||
|
|
.dat_out ( irdy_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg trdy_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( trdy_in ) ,
|
||
|
|
.en_in ( trdy_en_in ) ,
|
||
|
|
.en_out ( trdy_en_out ),
|
||
|
|
.dat_out ( trdy_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg stop_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( stop_in ) ,
|
||
|
|
.en_in ( stop_en_in ) ,
|
||
|
|
.en_out ( stop_en_out ),
|
||
|
|
.dat_out ( stop_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg devsel_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( devsel_in ) ,
|
||
|
|
.en_in ( devsel_en_in ) ,
|
||
|
|
.en_out ( devsel_en_out ),
|
||
|
|
.dat_out ( devsel_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg par_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( par_in ) ,
|
||
|
|
.en_in ( par_en_in ) ,
|
||
|
|
.en_out ( par_en_out ),
|
||
|
|
.dat_out ( par_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg perr_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( perr_in ) ,
|
||
|
|
.en_in ( perr_en_in ) ,
|
||
|
|
.en_out ( perr_en_out ),
|
||
|
|
.dat_out ( perr_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg serr_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( serr_in ) ,
|
||
|
|
.en_in ( serr_en_in ) ,
|
||
|
|
.en_out ( serr_en_out ),
|
||
|
|
.dat_out ( serr_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
pci_out_reg req_iob
|
||
|
|
(
|
||
|
|
.reset_in ( reset_in ),
|
||
|
|
.clk_in ( clk_in) ,
|
||
|
|
.dat_en_in ( 1'b1 ),
|
||
|
|
.en_en_in ( 1'b1 ),
|
||
|
|
.dat_in ( req_in ) ,
|
||
|
|
.en_in ( init_complete_in ) ,
|
||
|
|
.en_out ( req_en_out ),
|
||
|
|
.dat_out ( req_out )
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|