161 lines
6.0 KiB
Coq
161 lines
6.0 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: pci_in_reg.v ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: pci_in_reg.v,v $
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// Revision 1.5 2003/12/19 11:11:30 mihad
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// Compact PCI Hot Swap support added.
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// New testcases added.
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// Specification updated.
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// Test application changed to support WB B3 cycles.
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//
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// Revision 1.4 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:29 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "pci_constants.v"
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// Module is used for registering PCI input signals
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// It provides data flip flops with reset
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module pci_in_reg
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(
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reset_in,
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clk_in,
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init_complete_in,
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pci_gnt_in,
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pci_frame_in,
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pci_irdy_in,
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pci_trdy_in,
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pci_stop_in,
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pci_devsel_in,
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pci_idsel_in,
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pci_ad_in,
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pci_cbe_in,
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pci_gnt_reg_out,
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pci_frame_reg_out,
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pci_irdy_reg_out,
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pci_trdy_reg_out,
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pci_stop_reg_out,
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pci_devsel_reg_out,
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pci_idsel_reg_out,
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pci_ad_reg_out,
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pci_cbe_reg_out
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);
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input reset_in, clk_in, init_complete_in ;
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input pci_gnt_in ;
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input pci_frame_in ;
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input pci_irdy_in ;
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input pci_trdy_in ;
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input pci_stop_in ;
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input pci_devsel_in ;
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input pci_idsel_in ;
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input [31:0] pci_ad_in ;
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input [3:0] pci_cbe_in ;
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output pci_gnt_reg_out ;
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output pci_frame_reg_out ;
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output pci_irdy_reg_out ;
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output pci_trdy_reg_out ;
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output pci_stop_reg_out ;
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output pci_devsel_reg_out ;
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output pci_idsel_reg_out ;
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output [31:0] pci_ad_reg_out ;
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output [3:0] pci_cbe_reg_out ;
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reg pci_gnt_reg_out ;
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reg pci_frame_reg_out ;
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reg pci_irdy_reg_out ;
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reg pci_trdy_reg_out ;
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reg pci_stop_reg_out ;
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reg pci_devsel_reg_out ;
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reg pci_idsel_reg_out ;
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reg [31:0] pci_ad_reg_out ;
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reg [3:0] pci_cbe_reg_out ;
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always@(posedge reset_in or posedge clk_in)
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begin
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if ( reset_in )
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begin
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pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
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pci_frame_reg_out <= #`FF_DELAY 1'b0 ;
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pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
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pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
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pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
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pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
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pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
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pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
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end
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else if (init_complete_in)
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begin
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pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
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pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
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pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
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pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
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pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;
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pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;
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pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;
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pci_ad_reg_out <= #`FF_DELAY pci_ad_in ;
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pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
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end
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end
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endmodule
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