2019-07-08 17:18:08 -05:00
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# Standard Configuration Example
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[dir_path]
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script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
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benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
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yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
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odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
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cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
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abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
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abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
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m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
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mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
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vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
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rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
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ace_path = OPENFPGAPATHKEYWORD/ace2/ace
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2019-07-08 17:18:08 -05:00
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[flow_conf]
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flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
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2020-01-22 22:03:57 -06:00
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vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
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2019-07-08 17:18:08 -05:00
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mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
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m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
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2019-07-08 17:18:08 -05:00
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mpack2_arch = K6_pattern7_I24.arch
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2020-01-22 22:03:57 -06:00
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power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
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2019-07-08 17:18:08 -05:00
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[csv_tags]
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mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
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mpack2_tags = BLE Number:|BLE Fill Rate:
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vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
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vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
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