244 lines
10 KiB
C++
244 lines
10 KiB
C++
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/************************************************
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* This file includes most utilized functions for
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* generating Verilog sub-modules
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* such as timing matrix and signal initialization
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***********************************************/
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#include <fstream>
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#include <limits>
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#include <iomanip>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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/* Headers from readarchopenfpga library */
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#include "circuit_types.h"
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#include "module_manager_utils.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_submodule_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/* All values are printed with this precision value. The higher the
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* value, the more accurate timing assignment is. Using a number of 6
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* guarentees that a precision of femtosecond which is sufficent for
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* electrical simulation (simulation timescale is 10-9
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*/
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/* constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10; */
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constexpr int FLOAT_PRECISION = 6;
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/************************************************
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* Print a timing matrix defined in theecircuit model
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* into a Verilog format.
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* This function print all the timing edges available
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* in the circuit model (any pin-to-pin delay)
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***********************************************/
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void print_verilog_submodule_timing(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* return if there is no delay info */
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if ( 0 == circuit_lib.num_delay_info(circuit_model)) {
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return;
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}
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/* Return if there is no ports */
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if (0 == circuit_lib.num_model_ports(circuit_model)) {
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return;
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}
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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fp << std::endl;
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fp << "`ifdef " << VERILOG_TIMING_PREPROC_FLAG << std::endl;
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print_verilog_comment(fp, std::string("------ BEGIN Pin-to-pin Timing constraints -----"));
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fp << "\tspecify" << std::endl;
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/* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */
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for (const auto& timing_edge : circuit_lib.timing_edges_by_model(circuit_model)) {
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CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
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size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge);
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BasicPort src_port_info(circuit_lib.port_lib_name(src_port), src_pin, src_pin);
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CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
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size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge);
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BasicPort sink_port_info(circuit_lib.port_lib_name(sink_port), sink_pin, sink_pin);
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fp << "\t\t";
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fp << "(" << generate_verilog_port(VERILOG_PORT_CONKT, src_port_info);
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fp << " => ";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")";
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fp << " = ";
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fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_RISE) / VERILOG_SIM_TIMESCALE;
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fp << ", ";
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fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_FALL) / VERILOG_SIM_TIMESCALE << ")";
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fp << ";" << std::endl;
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}
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fp << "\tendspecify" << std::endl;
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print_verilog_comment(fp, std::string("------ END Pin-to-pin Timing constraints -----"));
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fp << "`endif" << std::endl;
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}
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void print_verilog_submodule_signal_init(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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fp << std::endl;
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fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
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print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
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fp << "\tinitial begin" << std::endl;
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fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
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/* Only for formal verification: deposite a zero signal values */
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/* Initialize each input port */
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for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
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BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
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fp << "\t\t$deposit(";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
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fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
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fp << ");" << std::endl;
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}
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fp << "\t`else" << std::endl;
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/* Regular case: deposite initial signal values: a random value */
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for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
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BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
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fp << "\t\t$deposit(";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
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fp << ", $random);" << std::endl;
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}
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fp << "\t`endif\n" << std::endl;
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fp << "\tend" << std::endl;
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print_verilog_comment(fp, std::string("------ END driver initialization -----"));
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fp << "`endif" << std::endl;
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}
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/*********************************************************************
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* Register all the user-defined modules in the module manager
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* Walk through the circuit library and add user-defined circuit models
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* to the module_manager
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********************************************************************/
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void add_user_defined_verilog_modules(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib) {
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/* Iterate over Verilog modules */
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for (const auto& model : circuit_lib.models()) {
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/* We only care about user-defined models */
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if (true == circuit_lib.model_verilog_netlist(model).empty()) {
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continue;
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}
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/* Skip Routing channel wire models because they need a different name. Do it later */
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if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
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continue;
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}
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/* Reach here, the model requires a user-defined Verilog netlist,
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* Try to find it in the module manager
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* If not found, register it in the module_manager
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*/
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ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model));
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if (ModuleId::INVALID() == module_id) {
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add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
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}
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}
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}
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/*********************************************************************
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* Print a template for a user-defined circuit model
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* The template will include just the port declaration of the Verilog module
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* The template aims to help user to write Verilog codes with a guaranteed
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* module definition, which can be correctly instanciated (with correct
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* port mapping) in the FPGA fabric
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********************************************************************/
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static
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void print_one_verilog_template_module(const ModuleManager& module_manager,
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std::fstream& fp,
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const std::string& module_name) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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print_verilog_comment(fp, std::string("----- Template Verilog module for " + module_name + " -----"));
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/* Find the module in module manager, which should be already registered */
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/* TODO: routing channel wire model may have a different name! */
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ModuleId template_module = module_manager.find_module(module_name);
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VTR_ASSERT(ModuleId::INVALID() != template_module);
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, template_module);
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/* Finish dumping ports */
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print_verilog_comment(fp, std::string("----- Internal logic should start here -----"));
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/* Add some empty lines as placeholders for the internal logic*/
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fp << std::endl << std::endl;
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print_verilog_comment(fp, std::string("----- Internal logic should end here -----"));
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_name);
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/*********************************************************************
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* Print a template of all the submodules that are user-defined
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* The template will include just the port declaration of the submodule
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* The template aims to help user to write Verilog codes with a guaranteed
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* module definition, which can be correctly instanciated (with correct
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* port mapping) in the FPGA fabric
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********************************************************************/
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void print_verilog_submodule_templates(const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir) {
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std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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/* Print out debugging information for if the file is not opened/created properly */
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VTR_LOG("Creating template for user-defined Verilog modules '%s'...",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Template for user-defined Verilog modules");
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Output essential models*/
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for (const auto& model : circuit_lib.models()) {
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/* Focus on user-defined modules, which must have a Verilog netlist defined */
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if (circuit_lib.model_verilog_netlist(model).empty()) {
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continue;
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}
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/* Skip Routing channel wire models because they need a different name. Do it later */
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if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
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continue;
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}
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/* Print a Verilog template for the circuit model */
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print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model));
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}
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/* close file stream */
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fp.close();
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/* No need to add the template to the subckt include files! */
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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