52 lines
3.1 KiB
C++
52 lines
3.1 KiB
C++
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/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate Verilog netlists modeling the full FPGA fabric
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* This is one of the core engine of openfpga, including:
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* - generate_fabric_verilog : generate Verilog netlists about FPGA fabric
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* - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches
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*******************************************************************/
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#include "openfpga_verilog.h"
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#include "openfpga_verilog_command.h"
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/* begin namespace openfpga */
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namespace openfpga {
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void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
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const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
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/********************************
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* Command 'wirte_fabric_verilog'
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*/
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Command shell_cmd_write_fabric_verilog("write_fabric_verilog");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId fabric_verilog_output_opt = shell_cmd_write_fabric_verilog.add_option("file", true, "Specify the output directory for Verilog netlists");
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shell_cmd_write_fabric_verilog.set_option_short_name(fabric_verilog_output_opt, "f");
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shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_output_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd_write_fabric_verilog.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* Add an option '--include_timing' */
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shell_cmd_write_fabric_verilog.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
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/* Add an option '--include_signal_init' */
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shell_cmd_write_fabric_verilog.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
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/* Add an option '--support_icarus_simulator' */
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shell_cmd_write_fabric_verilog.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
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/* Add an option '--verbose' */
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shell_cmd_write_fabric_verilog.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_write_fabric_verilog_id = shell.add_command(shell_cmd_write_fabric_verilog, "generate Verilog netlists modeling full FPGA fabric");
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shell.set_command_class(shell_cmd_write_fabric_verilog_id, openfpga_verilog_cmd_class);
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shell.set_command_execute_function(shell_cmd_write_fabric_verilog_id, write_fabric_verilog);
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/* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
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std::vector<ShellCommandId> cmd_dependency_write_fabric_verilog;
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cmd_dependency_write_fabric_verilog.push_back(shell_cmd_build_fabric_id);
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shell.set_command_dependency(shell_cmd_write_fabric_verilog_id, cmd_dependency_write_fabric_verilog);
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}
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} /* end namespace openfpga */
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