OpenFPGA/jupyter_example.ipynb

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    "# Getting Started with Jupyter and FPGA-SPICE on Linux\n",
    "\n",
    "1. Install Anaconda: https://conda.io/docs/user-guide/install/linux.html \n",
    "2. Run anaconda-navigator: `~/anaconda-navigator`\n",
    "3. Launch jupyter notebook from anaconda navigator\n",
    "\n",
    "In the jupyter interface, navigate to the location of a notebook and view it."
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "The repository contains a submodule, so you need to get it as well:"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Build the VPR tool with the FPGA-SPICE functionality:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 38,
   "metadata": {
    "scrolled": true
   },
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Wait for make to finish with a return code of 0.\n"
     ]
    },
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       "0"
      ]
     },
     "execution_count": 38,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "import os\n",
    "# move to the directory with the Makefile\n",
    "os.chdir(\"./tangxifan-eda-tools/branches/vpr7_rram/vpr/\")\n",
    "# run make\n",
    "print (\"Wait for make to finish with a return code of 0.\")\n",
    "os.system(\"make\")"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "To run FPGA-SPICE, define its location:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 39,
   "metadata": {},
   "outputs": [],
   "source": [
    "# set this to the location of the vpr executable file\n",
    "fpga_spice = \"~/OpenFPGA/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr\""
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Define an architecture file and a circuit file:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 40,
   "metadata": {},
   "outputs": [],
   "source": [
    "arch = \"./tutorial/example_arch.xml\"\n",
    "circuit = \"./tutorial/example_circuit.blif\""
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Run vpr:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 41,
   "metadata": {},
   "outputs": [
    {
     "data": {
      "text/plain": [
       "256"
      ]
     },
     "execution_count": 41,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "\n",
    "command_line = fpga_spice + \" \" + arch + \" \" + circuit\n",
    "os.system(command_line)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "This will bring up a graphical display of how the circuit is being placed on the FPGA. Press the `Proceed` button to step to the final placement, press `Proceed` again to step to the routing. Press the `Exit` button to exit the display.\n",
    "\n",
    "To run VPR without the display, use the command `-nodisp`"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 23,
   "metadata": {},
   "outputs": [],
   "source": [
    "command_line_nodisp = command_line + \" -nodisp\"\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 36,
   "metadata": {},
   "outputs": [
    {
     "data": {
      "text/plain": [
       "0"
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     },
     "execution_count": 36,
     "metadata": {},
     "output_type": "execute_result"
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   ],
   "source": [
    "os.system(command_line_nodisp)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "When you ran the tool, a number of text output files are created that report on what the tool did. Open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note on line 2: \n",
    "\n",
    "> `Array size: 2 x 2 logic blocks`\n",
    "\n",
    "This is a report that when the tool placed and routed the logic, it ended up in a 2 x 2 grid."
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Now open the file \"OpenFPGA/tutorial/example_arch.xml\" in a text editor. Go to line 51 and change:\n",
    "\n",
    "<pb_type name=\"io\" capacity=\"1\">\n",
    "\n",
    "to:\n",
    "\n",
    "<pb_type name=\"io\" capacity=\"3\">\n",
    "\n",
    "Now, instead of each input/output block only having 1 input or output, they can have 3 inputs or outputs.\n",
    "\n",
    "Run the tool again:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 34,
   "metadata": {},
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     "data": {
      "text/plain": [
       "0"
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     "execution_count": 34,
     "metadata": {},
     "output_type": "execute_result"
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   ],
   "source": [
    "os.system(command_line_nodisp)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Re-open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note that the logic is now placed in one block:\n",
    "\n",
    "> `Array size: 1 x 1 logic blocks`\n",
    "\n",
    "The simple change to the number of inputs or outputs per I/O block let the placement and routing tool use less space on the FPGA for the circuit."
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "# The Architecture format\n",
    "An FPGA architecture is specified in an XML file and is wrapped in an `<architecture>` tag. `example_arch.xml` defines a simple FPGA.\n",
    "\n",
    "Line 18 has the `<models>` tag which would describe `BLIF` circuit model names that the FPGA accepts. This architecture is simple enough to not need any additional models beyond the default `.names .latch .input .output`.\n",
    "\n",
    "Line 23 has the `<layout>` tag which specifies how the FPGA grid will be laid out. For this example: `<layout auto=\"1.000000\"/>` specifies an automatic grid with an aspect ratio of 1.0. A specific width and heigh could be specified instead of the automatic layout.\n",
    "\n",
    "Line 24 begins the `<device>` tag which characterizes the components of the FPGA. `<sizing>` specifies the resistance of the minimum-width nmos and pmos transistors. `<area grid_logic_tile_area>` is used as an estimate of the size of one grid tile.\n",
    "\n",
    "Line 28 is the `<chan_width_distr>` section which sets the relative widths of the routing channels in various parts of the FPGA. Here, all channels are set to be distrubuted uniformly.\n",
    "\n",
    "Line 33 is the `<switch_block>` tag which specifies the pattern of the switches used to connect the block routing segments. \n",
    "\n",
    "Line 35 is the `<switchlist>` section which specifies the switches used to connect wires and pins together. Resistance, in/out capacitance, delay through the switch, and component size.\n",
    "\n",
    "Line 38 is the `<segmentlist>` section that specifies kinds of wire segments and their properties such as resistance and capacitance. `<sb type=\"pattern\">1 1</sb>` describes a pattern on a 1-length wire where there is a switch box between each grid element. `<cb type=\"pattern\">1</cb>` describes a pattern on a 1-length wire where there is a connection box at each grid element.\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  }
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