76 lines
2.6 KiB
C++
76 lines
2.6 KiB
C++
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/********************************************************************
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* This file includes functions that are used to print the top-level
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* module for the FPGA fabric in Verilog format
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*******************************************************************/
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#include <fstream>
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#include <map>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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#include "verilog_top_module.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print the top-level module for the FPGA fabric in Verilog format
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* This function will
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* 1. name the top-level module
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* 2. include dependent netlists
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* - User defined netlists
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* - Auto-generated netlists
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* 3. Add the submodules to the top-level graph
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* 4. Add module nets to connect datapath ports
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* 5. Add module nets/submodules to connect configuration ports
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*******************************************************************/
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void print_verilog_top_module(const ModuleManager& module_manager,
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const std::string& verilog_dir,
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const bool& use_explicit_mapping) {
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/* Create a module as the top-level fabric, and add it to the module manager */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(top_module));
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/* Start printing out Verilog netlists */
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/* Create the file name for Verilog netlist */
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std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
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VTR_LOG("Writing Verilog netlist for top-level module of FPGA fabric '%s'...",
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verilog_fname.c_str());
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA"));
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/* Print preprocessing flags */
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Write the module content in Verilog format */
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write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping);
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/* Add an empty line as a splitter */
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fp << std::endl;
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/* Close file handler */
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fp.close();
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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