2020-02-16 13:45:58 -06:00
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#ifndef VERILOG_LUT_H
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#define VERILOG_LUT_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include <string>
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#include "circuit_library.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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2020-02-16 17:35:26 -06:00
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void print_verilog_submodule_luts(const ModuleManager& module_manager,
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2020-02-16 13:45:58 -06:00
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std::vector<std::string>& netlist_names,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir,
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const bool& use_explicit_port_map);
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} /* end namespace openfpga */
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#endif
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