OpenFPGA/docs/source/z_reference.bib

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@INPROCEEDINGS{XTang_ICCD_2015,
author={X. Tang and P. Gaillardon and G. De Micheli},
booktitle={2015 33rd IEEE International Conference on Computer Design (ICCD)},
title={FPGA-SPICE: A simulation-based power estimation framework for FPGAs},
year={2015},
volume={},
number={},
pages={696-703},
keywords={circuit simulation;field programmable gate arrays;logic design;power consumption;SPICE;table lookup;flip-flops;global routing architecture;circuit elements;grid-level testbenches;full-chip-level testbenches;component-level testbenches;architectural description language;LUTs;FPGAs routing multiplexers;look up tables;power consumption;analytical power models;probabilistic activity estimation;field programmable gate array;simulation-based power estimation framework;FPGA-SPICE;Field programmable gate arrays;Routing;Integrated circuit modeling;Estimation;SPICE;Table lookup},
doi={10.1109/ICCD.2015.7357183},
ISSN={},
month={Oct},}

@ARTICLE{XTang_JETCAS_2018,
author={X. Tang and E. Giacomin and G. De Micheli and P. Gaillardon},
journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
title={Post-P amp;R Performance and Power Analysis for RRAM-Based FPGAs},
year={2018},
volume={8},
number={3},
pages={639-650},
keywords={Field programmable gate arrays;Random access memory;Analytical models;Delays;Resistance;Routing;Programmable logic arrays;resistive ram;simulation;system modeling;integrated circuit reliability},
doi={10.1109/JETCAS.2018.2847600},
ISSN={2156-3357},
month={Sept},}

@book{VBetz_Book_1999,
 editor = {Betz, Vaughn and Rose, Jonathan and Marquardt, Alexander},
 title = {Architecture and CAD for Deep-Submicron FPGAs},
 year = {1999},
 isbn = {0792384601},
 publisher = {Kluwer Academic Publishers},
 address = {Norwell, MA, USA},
} 

@article{XTang_TCAS1_2016,
	title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}},
	author={Tang, Xifan and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
	journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
	volume={63},
	number={4},
	pages={503--516},
	year={2016},
	publisher={IEEE}
}


@ARTICLE{XTang_TCAS1_2017,
	author={X. Tang and E. Giacomin and G. De Micheli and P. E. Gaillardon},
	journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
	title={{Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure}},
	year={2017},
	volume={64},
	number={5},
	pages={1173-1186},
	keywords={Delays;Logic gates;Multiplexing;Programming;Resistance;Routing;Transistors;Circuit design;high-performance;low-power;multiplexer;resistive memory},
	doi={10.1109/TCSI.2016.2638542},
	ISSN={1549-8328},
	month={May},}

@inproceedings{JLuu_FPGA_2011,
	author = {Luu, Jason and Anderson, Jason Helge and Rose, Jonathan Scott},
	title = {{Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect}},
	booktitle = {Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
	series = {FPGA '11},
	year = {2011},
	isbn = {978-1-4503-0554-9},
	location = {Monterey, CA, USA},
	pages = {227--236},
	numpages = {10},
	url = {http://doi.acm.org/10.1145/1950413.1950457},
	doi = {10.1145/1950413.1950457},
	acmid = {1950457},
	publisher = {ACM},
	address = {New York, NY, USA},
	keywords = {architecture description language, clustering, complex block, configurable memory, configurable multiplier, fpga, hard logic cluster, logic block, logic cluster, packing, soft logic cluster, splitting},
} 

@INPROCEEDINGS{JGoeders_FPT_2012,
	author={J. B. Goeders and S. J. E. Wilton},
	booktitle={2012 International Conference on Field-Programmable Technology},
	title={{VersaPower: Power Estimation for Diverse FPGA Architectures}},
	year={2012},
	pages={229-234},
	keywords={CMOS integrated circuits;SPICE;computer architecture;field programmable gate arrays;logic CAD;CMOS technology;HDL;SPICE;VPR;VersaPower;Versatile Place and Route 6.0;academic FPGA CAD tool;complex logic block;diverse FPGA architecture;field programmable gate array;fracturable look-up table;power consumption;power estimation;size 130 nm;size 22 nm;size 45 nm;Capacitance;Field programmable gate arrays;Multiplexing;Solid modeling;Table lookup;Transistors;Wires},
	doi={10.1109/FPT.2012.6412139},
	month={Dec},}

@inproceedings{JRose_FPGA_2012,
   author = {Rose, Jonathan and Luu, Jason and Yu, Chi Wai and Densmore, Opal and Goeders, Jeffrey and Somerville, Andrew and Kent, Kenneth B. and Jamieson, Peter and Anderson, Jason},
   title = {{The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing}},
   booktitle = {Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
   series = {FPGA '12},
   year = {2012},
   isbn = {978-1-4503-1155-7},
   location = {Monterey, California, USA},
   pages = {77--86},
   numpages = {10},
   url = {http://doi.acm.org/10.1145/2145694.2145708},
   doi = {10.1145/2145694.2145708},
   acmid = {2145708},
   publisher = {ACM},
   address = {New York, NY, USA},
   keywords = {CAD, FPGA, architecture},
}