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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h

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refactoring Verilog generation for routing channels
2019-09-16 18:35:51 -05:00
/***********************************************
* Header file for verilog_routing.cpp
**********************************************/
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 21:11:22 -05:00
#ifndef VERILOG_ROUTING_H
#define VERILOG_ROUTING_H
refactoring Verilog generation for routing channels
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/* Include other header files which are dependency on the function declared below */
start refactoring the switch block verilog generation
2019-09-17 21:40:26 -05:00
#include "mux_library.h"
refactoring Verilog generation for routing channels
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#include "module_manager.h"
add module nets to connect grids and sbs
2019-10-15 17:08:51 -05:00
#include "rr_blocks.h"
refactoring Verilog generation for routing channels
2019-09-16 18:35:51 -05:00
refactored routing module generation and verilog writing
2019-10-23 12:46:55 -05:00
void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const t_det_routing_arch& routing_arch,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
void print_verilog_unique_routing_modules(ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const t_det_routing_arch& routing_arch,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 21:11:22 -05:00
#endif