2019-07-10 11:03:30 -05:00
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# Tutorial introduction
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OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.<br />
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Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.<br /><br />
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These tutorials are organized as follow:
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2019-07-15 22:16:15 -05:00
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* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
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* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
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2019-07-10 11:03:30 -05:00
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* Architecture modification
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## Folder organization
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OpenFPGA repository is organized as follow:
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* **abc**: open source synthesys tool
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* **ace2**: abc extension generating .act files
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* **vpr7_x2p**: sources of modified vpr
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* **yosys**: opensource synthesys tool
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* **fpga_flow**: scripts and dependencies to run the complete flow
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## Tips and informations
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Some keywords will be used during this tutorial:
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* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path
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