18 lines
1.2 KiB
Markdown
18 lines
1.2 KiB
Markdown
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# Naming convention for VPR architecture files
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Please reveal the following architecture features in the names to help quickly spot architecture files.
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- k<lut\_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
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- frac: If fracturable LUT is used or not.
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- N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
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- tileable: If the routing architecture is tileable or not.
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- adder\_chain: If hard adder/carry chain is used inside CLBs
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- register\_chain: If shift register chain is used inside CLBs
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- scan\_chain: If scan chain testing infrastructure is used inside CLBs
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- <wide>\_mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
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- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
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- multi\_io\_capacity: If I/O capacity is different on each side of FPGAs.
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- reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs
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- <feature_size>: The technology node which the delay numbers are extracted from.
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Other features are used in naming should be listed here.
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