2019-08-09 17:49:05 -05:00
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# Standard Configuration Example
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[CAD_TOOLS_PATH]
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yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
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misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
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odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
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abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc
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abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
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abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
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vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr
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ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
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2019-08-15 15:39:58 -05:00
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pro_blif_path = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/pro_blif.pl
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iverilog_path = iverilog
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include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists
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2019-08-09 17:49:05 -05:00
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[OPENFPGA_FLOW_CONFIG]
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# You dont need to change any of these varaibles,
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# Unless you are unhappy with intermidiate directories
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# or modifying fpga_flow sript significantly
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supported_flows = standard,vtr,vtr_standard,yosys_vpr
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2019-08-15 15:39:58 -05:00
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[DEFAULT_PARSE_RESULT_VPR]
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# parser format <name of variable> = <regex string>, <lambda function/type>
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clb_blocks = "Netlist clb blocks: ([0-9]+)", int
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logic_delay = "Total logic delay: ([0-9.]+)", str
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total_net_delay = "total net delay: ([0-9.]+)", str
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total_routing_area = "Total routing area: ([0-9.]+)", str
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total_logic_block_area = "Total used logic block area: ([0-9]+)", str
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total_wire_length = "Total wirelength: ([0-9]+)", str
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packing_time = "Packing took ([0-9.]+) seconds", str
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placement_time = "Placement took ([0-9.]+) seconds", str
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routing_time = "Routing took ([0-9.]+) seconds", str
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average_net_length = "average net length: ([0-9.]+)", str
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critical_path = "Final critical path: ([0-9.]+) ns", float
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total_time_taken = "Routing took ([0-9.]+) seconds", float
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[DEFAULT_PARSE_RESULT_POWER]
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pb_type_power="PB Types\s+([0-9]+)", float
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routing_power="Routing\s+([0-9]+)", float
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switch_box_power="Switch Box\s+([0-9]+)", float
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connection_box_power="Connection Box\s+([0-9]+)", float
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primitives_power="Primitives\s+([0-9]+)", float
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interc_structures_power="Interc Structures\s+([0-9]+)", float
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lut6_power="^\s+lut6\s+([0-9]+)", float
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ff_power="^\s+ff\s+([0-9]+)", float
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[INTERMIDIATE_FILE_PREFIX]
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