# Standard Configuration Example [CAD_TOOLS_PATH] yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace pro_blif_path = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/pro_blif.pl iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists [OPENFPGA_FLOW_CONFIG] # You dont need to change any of these varaibles, # Unless you are unhappy with intermidiate directories # or modifying fpga_flow sript significantly supported_flows = standard,vtr,vtr_standard,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , clb_blocks = "Netlist clb blocks: ([0-9]+)", int logic_delay = "Total logic delay: ([0-9.]+)", str total_net_delay = "total net delay: ([0-9.]+)", str total_routing_area = "Total routing area: ([0-9.]+)", str total_logic_block_area = "Total used logic block area: ([0-9]+)", str total_wire_length = "Total wirelength: ([0-9]+)", str packing_time = "Packing took ([0-9.]+) seconds", str placement_time = "Placement took ([0-9.]+) seconds", str routing_time = "Routing took ([0-9.]+) seconds", str average_net_length = "average net length: ([0-9.]+)", str critical_path = "Final critical path: ([0-9.]+) ns", float total_time_taken = "Routing took ([0-9.]+) seconds", float [DEFAULT_PARSE_RESULT_POWER] pb_type_power="PB Types\s+([0-9]+)", float routing_power="Routing\s+([0-9]+)", float switch_box_power="Switch Box\s+([0-9]+)", float connection_box_power="Connection Box\s+([0-9]+)", float primitives_power="Primitives\s+([0-9]+)", float interc_structures_power="Interc Structures\s+([0-9]+)", float lut6_power="^\s+lut6\s+([0-9]+)", float ff_power="^\s+ff\s+([0-9]+)", float [INTERMIDIATE_FILE_PREFIX]