69 lines
2.4 KiB
SourcePawn
69 lines
2.4 KiB
SourcePawn
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Testbench for D-type Flip-flop with set and reset
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*********************************
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* HSPICE Netlist *
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* Author: Xifan TANG *
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* Organization: EPFL,LSI *
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*********************************
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*
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* Use Standard CMOS Technology
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****** Include Technology Library ******
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.lib '/home/xitang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel_crn45gs_2d5_v1d1_shrink0d9_embedded_usage.l' TOP_TT
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****** Transistor Parameters ******
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.param beta=2
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.param nl=4e-08
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.param wn=1.4e-07
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.param pl=4e-08
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.param wp=1.4e-07
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****** Include subckt netlists: NMOS and PMOS *****
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.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/nmos_pmos.sp'
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****** Include subckt netlists: Inverters, Buffers *****
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.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/inv_buf_trans_gate.sp'
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.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
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.param clk_freq = 1e9
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*Temperature
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.temp 25
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*Global nodes
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.global vdd gnd
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*Print node capacitance
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.option captab
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*Print waveforms
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.option POST
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* Parameters for measurements
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.param clk2d=3e-09
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.param clk_pwl=3e-09
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.param clk_pwh=1.5e-08
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.param slew=1e-11
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.param thold=3e-09
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.param vsp=0.9
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* Parameters for Measuring Slew
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.param slew_upper_threshold_pct_rise=0.9
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.param slew_lower_threshold_pct_rise=0.1
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.param slew_upper_threshold_pct_fall=0.1
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.param slew_lower_threshold_pct_fall=0.9
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* Parameters for Measuring Delay
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.param input_threshold_pct_rise=0.5
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.param input_threshold_pct_fall=0.5
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.param output_threshold_pct_rise=0.5
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.param output_threshold_pct_fall=0.5
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Xdff[0] set rst clk d q vdd gnd static_dff
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Vsupply vdd gnd 'vsp'
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*Stimulates
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vset set gnd 0
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vrst rst gnd 0
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vclk_in clk gnd pulse (0 vsp '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq' '1/clk_freq')
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* Measuring Clk2Q, Setup Time and Hold Time
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vdata D gnd pulse (0 vsp '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '2*0.4875/clk_freq' '2/clk_freq')
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*Simulation
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.tran 1e-15 '10/clk_freq'
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.meas tran slew_q trig v(Q) val='slew_lower_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
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+ targ v(Q) val='slew_upper_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
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.meas tran clk2q trig v(CLK) val='input_threshold_pct_fall*vsp' rise=2
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+ targ v(Q) val='output_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
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.end TSPC Flip-flop with set and reset
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