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OpenFPGA/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h

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Refactored Verilog wiring for formal verification ports in Switch Blocks
2019-09-27 14:51:22 -05:00
/********************************************************************
* Header file for circuit_library_utils.cpp
*******************************************************************/
#ifndef CIRCUIT_LIBRARY_UTILS_H
#define CIRCUIT_LIBRARY_UTILS_H
/* Header files should be included in a sequence */
/* Standard header files required go first */
#include <vector>
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
2019-10-08 19:00:04 -05:00
#include "spice_types.h"
Refactored Verilog wiring for formal verification ports in Switch Blocks
2019-09-27 14:51:22 -05:00
#include "circuit_library.h"
refactored local encoder support for Verilog MUX generation
2019-09-28 00:10:43 -05:00
std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
Refactored Verilog wiring for formal verification ports in Switch Blocks
2019-09-27 14:51:22 -05:00
refactorint net addition for configuration signals in module graph
2019-10-11 14:07:14 -05:00
std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
2019-10-08 19:00:04 -05:00
size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model,
const e_sram_orgz& sram_orgz_type);
size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
added Verilog generation for preconfig top module
2019-10-29 14:54:35 -05:00
std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
refactored include netlist writer
2019-11-04 21:55:30 -06:00
std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
Refactored Verilog wiring for formal verification ports in Switch Blocks
2019-09-27 14:51:22 -05:00
#endif