tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
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6bed89c237
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refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
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tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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dbe1625267
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Refactored Verilog wiring for formal verification ports in Switch Blocks
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2019-09-27 13:51:22 -06:00 |