OpenFPGA/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt

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bram $__MY_DPRAM
init 0
abits 10
dbits 32
groups 2
ports 1 1
wrmode 1 0
enable 1 1
transp 0 0
clocks 1 1
clkpol 1 1
endbram
bram $__MY_SPRAM
init 0
abits 10
dbits 32
groups 2
ports 1 1
wrmode 1 0
enable 1 0
transp 0 0
clocks 1 1
clkpol 1 1
endbram
match $__MY_DPRAM
min efficiency 0
make_transp
or_next_if_better
endmatch
match $__MY_SPRAM
min efficiency 0
make_transp
endmatch