2021-06-15 15:16:31 -05:00
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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2021-10-30 20:03:59 -05:00
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
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2021-06-15 15:16:31 -05:00
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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2021-07-01 14:52:28 -05:00
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openfpga_vpr_device_layout=
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openfpga_fast_configuration=
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2021-06-15 15:16:31 -05:00
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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2021-07-01 14:52:28 -05:00
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
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2021-07-01 16:35:39 -05:00
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
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2021-06-15 15:16:31 -05:00
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[SYNTHESIS_PARAM]
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2021-07-01 14:52:28 -05:00
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bench0_top = clock_divider
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bench0_chan_width = 300
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2021-07-01 16:35:39 -05:00
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bench1_top = pulse_generator
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bench1_chan_width = 300
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2021-07-01 14:52:28 -05:00
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2021-07-01 16:35:39 -05:00
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bench2_top = reset_generator
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bench2_chan_width = 300
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2021-06-15 15:16:31 -05:00
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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2021-10-30 20:03:59 -05:00
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#end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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