20 lines
318 B
Plaintext
20 lines
318 B
Plaintext
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#read design
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read_verilog -nolatches ../vpr7_x2p/vpr/Circuits/fifo_1bit.v
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# synth
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hierarchy -top fifo_1bit
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proc
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# Tech map
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techmap -D NO_LUT -map ./techlibs/common/adff2dff.v
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synth -top fifo_1bit -flatten
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clean
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abc -lut 6
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synth -run check
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opt_clean -purge
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write_blif ../vpr7_x2p/vpr/Circuits/fifo_1bit.blif
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