OpenFPGA/vpr7_x2p/vpr/Circuits
AurelienUoU 7ff245448b Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
..
fifo_1bit.act adapt arch xml and act for demo 2018-12-13 22:46:40 -07:00
fifo_1bit.blif add a benchmark fifo 2018-12-12 16:45:33 -07:00
fifo_1bit.v add a benchmark fifo 2018-12-12 16:45:33 -07:00
fifo_1bit.ys add a benchmark fifo 2018-12-12 16:45:33 -07:00
pip_add.act Add pip_add benchmark 2018-12-11 15:29:48 -07:00
pip_add.blif Add pip_add benchmark 2018-12-11 15:29:48 -07:00
pip_add.v Update go.sh and upload pip_add.v 2018-12-11 15:47:05 -07:00
s298_prevpr.act rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
s298_prevpr.blif rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
sync_4bits_add.act Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
sync_4bits_add.blif Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00
sync_4bits_add.v Add new benchmark and modify go.sh to use it 2018-12-26 04:24:26 -07:00