15 lines
1.5 KiB
ReStructuredText
15 lines
1.5 KiB
ReStructuredText
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EDA flow
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========
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As illustrated in Figure 1, FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis needs the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in Section V). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results, when enabled by command-line options. (See Section IV for details about command-line options.) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See Section VII for guidelines in customize your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e. HSPICE, can be called to conduct power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See Section VIII).
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.. figure:: figures/eda_flow.png
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:scale: 50 %
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:alt: map to buried treasure
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How to compile
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==============
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Running the Makefile in the released package can compile all the source codes.
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The released package includes a version of VPR with FPGA-SPICE support, ABC with black box support and Activity Estimator.
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