46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
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/*********************************************************************
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* The following code is part of the power modelling feature of VTR.
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*
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* For support:
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* http://code.google.com/p/vtr-verilog-to-routing/wiki/Power
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*
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* or email:
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* vtr.power.estimation@gmail.com
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*
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* If you are using power estimation for your researach please cite:
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*
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* Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation
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* for Diverse FPGA Architectures. In International Conference on
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* Field Programmable Technology, 2012.
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*
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********************************************************************/
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/**
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* The functions in this file are used to count the transistors in the
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* FPGA, for physical size estimations
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*/
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#ifndef __POWER_TRANSISTOR_CNT_H__
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#define __POWER_TRANSISTOR_CNT_H__
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/************************* INCLUDES *********************************/
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#include "physical_types.h"
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/************************* DEFINES **********************************/
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/* Design rules, values in LAMBDA, where tech size = 2 LAMBDA */
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#define POWER_DRC_MIN_L 2.0
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#define POWER_DRC_MIN_W 5.0
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#define POWER_DRC_MIN_DIFF_L 5.5
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#define POWER_DRC_SPACING 3.0
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#define POWER_DRC_POLY_OVERHANG 2.5
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#define POWER_MTA_W (POWER_DRC_MIN_W + POWER_DRC_POLY_OVERHANG + POWER_DRC_SPACING)
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#define POWER_MTA_L (POWER_DRC_MIN_L + 2 * POWER_DRC_MIN_DIFF_L + POWER_DRC_SPACING)
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/************************* FUNCTION DECLARATION *********************/
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void power_sizing_init(t_arch * arch);
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double power_count_transistors_buffer(float buffer_size);
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double power_transistor_area(double num_transistors);
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#endif
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