OpenFPGA/README.md

# Getting Started with FPGA-SPICE

[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
[![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)

## Introduction

FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.

## Compilation

The different ways of compiling can be found in the **./compilation** folder. 

We currently implemented it for:

1. Ubuntu 18.04
2. Red Hat 7.5
3. MacOS High Sierra 10.13.4

Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.

## Documentation
OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.

## Examples

You can find in the folder **./examples**. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them. 

./example_x.sh allows to launch the script linked to example_x.xml and .blif.

In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base. 

Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file.

Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added.
creating documentation 2018-09-13 12:52:12 -05:00			`# Getting Started with FPGA-SPICE`

Update README.md 2018-12-30 15:35:07 -06:00			`[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)`
			`[![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)`

Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`## Introduction`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`## Compilation`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`The different ways of compiling can be found in the ./compilation folder.`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`We currently implemented it for:`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`1. Ubuntu 18.04`
			`2. Red Hat 7.5`
			`3. MacOS High Sierra 10.13.4`
creating documentation 2018-09-13 12:52:12 -05:00
Update README.md Small correction 2018-12-05 17:27:37 -06:00			`Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.`
ReadMe modifications to add the beginning of the FPGA-SPICE tutorial Modifications on the addresses aswell and the different commands when they were not working. To do still: -create a script to change the addresses when needed -continue the tutorial 2018-09-27 10:33:39 -05:00
Update README.md 2018-12-30 15:37:17 -06:00			`## Documentation`
			`OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.`

Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`## Examples`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`You can find in the folder ./examples. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them.`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`./example_x.sh allows to launch the script linked to example_x.xml and .blif.`
creating documentation 2018-09-13 12:52:12 -05:00
Update of the Readme and added an example ReadMe is now cleaner 2018-10-03 18:10:29 -05:00			`In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base.`

Addition of the second example and a ReadME to understand them. Also: - Figures were added 2018-10-09 15:42:15 -05:00			`Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file.`
creating documentation 2018-09-13 12:52:12 -05:00
Addition of the second example and a ReadME to understand them. Also: - Figures were added 2018-10-09 15:42:15 -05:00			`Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added.`
ReadMe modifications to add the beginning of the FPGA-SPICE tutorial Modifications on the addresses aswell and the different commands when they were not working. To do still: -create a script to change the addresses when needed -continue the tutorial 2018-09-27 10:33:39 -05:00


creating documentation 2018-09-13 12:52:12 -05:00