72 lines
2.8 KiB
C++
72 lines
2.8 KiB
C++
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/********************************************************************
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* This file includes functions that outputs a circuit library to XML format
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*******************************************************************/
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/* Headers from system goes first */
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#include <string>
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/* Headers from vtr util library */
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#include "vtr_log.h"
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#include "openfpga_digest.h"
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/* Headers from readarchopenfpga library */
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#include "write_xml_utils.h"
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#include "write_xml_circuit_library.h"
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/********************************************************************
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* A writer to output a circuit model to XML format
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*******************************************************************/
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static
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void write_xml_circuit_model(std::fstream& fp,
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const char* fname,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& model) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the definition of circuit model */
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fp << "\t\t" << "<circuit_model";
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write_xml_attribute(fp, "type", CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(model)]);
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write_xml_attribute(fp, "name", circuit_lib.model_name(model).c_str());
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write_xml_attribute(fp, "prefix", circuit_lib.model_prefix(model).c_str());
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if (true == circuit_lib.model_is_default(model)) {
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write_xml_attribute(fp, "is_default", "true");
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}
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if (true == circuit_lib.dump_structural_verilog(model)) {
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write_xml_attribute(fp, "dump_structural_verilog", "true");
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}
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if (!circuit_lib.model_circuit_netlist(model).empty()) {
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write_xml_attribute(fp, "circuit_netlist", circuit_lib.model_circuit_netlist(model).c_str());
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}
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if (!circuit_lib.model_verilog_netlist(model).empty()) {
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write_xml_attribute(fp, "verilog_netlist", circuit_lib.model_verilog_netlist(model).c_str());
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}
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fp << ">" << "\n";
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/* Put an end to the XML definition of this circuit model */
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fp << "\t\t" << "</circuit_model>\n";
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}
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/********************************************************************
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* A writer to output a circuit library to XML format
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*******************************************************************/
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void write_xml_circuit_library(std::fstream& fp,
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const char* fname,
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const CircuitLibrary& circuit_lib) {
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/* Validate the file stream */
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openfpga::check_file_stream(fname, fp);
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/* Write the root node for circuit_library,
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* we apply a tab becuase circuit library is a subnode
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* under the root node <openfpga_arch>
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*/
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fp << "\t" << "<circuit_library>" << "\n";
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/* Write circuit model one by one */
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for (const CircuitModelId& model : circuit_lib.models()) {
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write_xml_circuit_model(fp, fname, circuit_lib, model);
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}
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/* Write the root node for circuit_library */
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fp << "\t" << "</circuit_library>" << "\n";
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}
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