469 lines
16 KiB
C
469 lines
16 KiB
C
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/***********************************/
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/* SPICE Modeling for VPR */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <time.h>
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#include <assert.h>
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#include <sys/stat.h>
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#include <unistd.h>
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/* Include vpr structs*/
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#include "util.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "globals.h"
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#include "rr_graph.h"
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#include "rr_graph_swseg.h"
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#include "vpr_utils.h"
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/* Include spice support headers*/
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#include "linkedlist.h"
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#include "fpga_spice_globals.h"
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#include "spice_globals.h"
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#include "fpga_spice_utils.h"
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#include "spice_utils.h"
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#include "spice_pbtypes.h"
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#include "spice_primitives.h"
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enum e_ff_trigger_type {
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FF_RE, FF_FE
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};
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/* Subroutines */
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void fprint_pb_primitive_ff(FILE* fp,
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char* subckt_prefix,
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t_logical_block* mapped_logical_block,
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t_pb_graph_node* prim_pb_graph_node,
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int index,
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t_spice_model* spice_model) {
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int i;
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/* Default FF settings, applied when this FF is idle*/
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enum e_ff_trigger_type trigger_type = FF_RE;
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int init_val = 0;
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int num_input_port = 0;
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t_spice_model_port** input_ports = NULL;
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int num_output_port = 0;
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t_spice_model_port** output_ports = NULL;
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int num_clock_port = 0;
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t_spice_model_port** clock_ports = NULL;
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int iport, ipin;
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int num_pb_type_output_port = 0;
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t_port** pb_type_output_ports = NULL;
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char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
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t_pb_type* prim_pb_type = NULL;
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char* port_prefix = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Ensure a valid pb_graph_node */
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if (NULL == prim_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find ports*/
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input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, FALSE);
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output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, FALSE);
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/* Asserts */
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assert(3 == num_input_port); /* D, Set and Reset*/
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for (i = 0; i < num_input_port; i++) {
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assert(1 == input_ports[i]->size);
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}
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assert(1 == num_output_port);
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assert(1 == output_ports[0]->size);
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assert(1 == num_clock_port);
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assert(1 == clock_ports[0]->size);
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assert(SPICE_MODEL_FF == spice_model->type);
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/* Initialize */
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prim_pb_type = prim_pb_graph_node->pb_type;
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if (NULL != mapped_logical_block) {
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fprintf(fp, "***** Logical block mapped to this FF: %s *****\n",
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mapped_logical_block->name);
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}
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/* Generate Subckt for pb_type*/
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/*
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index);
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*/
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/* Simplify the port prefix, make SPICE netlist readable */
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index);
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/* Definition line */
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fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix);
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/* print ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
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/* Local vdd and gnd*/
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fprintf(fp, "svdd sgnd\n");
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/* Definition ends*/
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/* Call the dff subckt*/
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fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt);
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/* Global ports */
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if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) {
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fprintf(fp, "+ ");
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}
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/* print ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); /* Use global clock for each DFF...*/
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/* Local vdd and gnd, spice_model name
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* global vdd for ff
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*/
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fprintf(fp, "%s_%s[%d] sgnd %s\n",
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spice_tb_global_vdd_port_name,
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spice_model->prefix,
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spice_model->cnt,
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spice_model->name);
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/* Apply rising edge, and init value to the ff*/
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if (NULL != mapped_logical_block) {
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/* Consider the rising edge|falling edge */
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if (0 == strcmp("re", mapped_logical_block->trigger_type)) {
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trigger_type = FF_RE;
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} else if (0 == strcmp("fe", mapped_logical_block->trigger_type)) {
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trigger_type = FF_FE;
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} else {
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vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid ff trigger type! Should be [re|fe].\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Assign initial value */
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if (1 == mapped_logical_block->init_val) {
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init_val = 1;
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} else {
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init_val = 0;
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}
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/* Back-annotate to logical block */
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mapped_logical_block->mapped_spice_model = spice_model;
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mapped_logical_block->mapped_spice_model_index = spice_model->cnt;
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} else {
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trigger_type = FF_RE;
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init_val = 0;
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}
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/* TODO: apply falling edge, initial value to FF!!!*/
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/*fprintf(fp, "\n");*/
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/* Add nodeset */
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pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(prim_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port);
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for (iport = 0; iport < num_pb_type_output_port; iport++) {
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for (ipin = 0; ipin < pb_type_output_ports[iport]->num_pins; ipin++) {
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fprintf(fp, ".nodeset V(%s->%s[%d]) ", port_prefix, pb_type_output_ports[iport]->name, ipin);
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if (0 == init_val) {
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fprintf(fp, "0\n");
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} else {
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assert(1 == init_val);
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fprintf(fp, "vsp\n");
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}
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}
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}
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/* End */
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fprintf(fp, ".eom\n");
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spice_model->cnt++;
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/*Free*/
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my_free(formatted_subckt_prefix);
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my_free(port_prefix);
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return;
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}
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/* Print hardlogic SPICE subckt*/
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void fprint_pb_primitive_hardlogic(FILE* fp,
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char* subckt_prefix,
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t_logical_block* mapped_logical_block,
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t_pb_graph_node* prim_pb_graph_node,
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int index,
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t_spice_model* spice_model) {
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int num_input_port = 0;
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t_spice_model_port** input_ports = NULL;
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int num_output_port = 0;
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t_spice_model_port** output_ports = NULL;
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int num_clock_port = 0;
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t_spice_model_port** clock_ports = NULL;
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char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
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t_pb_type* prim_pb_type = NULL;
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char* port_prefix = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Ensure a valid pb_graph_node */
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if (NULL == prim_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find ports*/
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input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE);
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/* Asserts */
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assert(SPICE_MODEL_HARDLOGIC == spice_model->type);
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/* Initialize */
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prim_pb_type = prim_pb_graph_node->pb_type;
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if (NULL != mapped_logical_block) {
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fprintf(fp, "***** Logical block mapped to this hardlogic: %s *****\n",
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mapped_logical_block->name);
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}
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/* Generate Subckt for pb_type*/
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/*
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index);
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*/
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/* Simplify the port prefix, make SPICE netlist readable */
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port_prefix = (char*)my_malloc(sizeof(char)*
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(strlen(prim_pb_type->name) + 1
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+ strlen(my_itoa(index)) + 1 + 1));
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sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index);
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/* Definition line */
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fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix);
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/* print ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
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/* Local vdd and gnd*/
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fprintf(fp, "svdd sgnd\n");
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/* Definition ends*/
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/* Back-annotate to logical block */
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if (NULL != mapped_logical_block) {
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mapped_logical_block->mapped_spice_model = spice_model;
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mapped_logical_block->mapped_spice_model_index = spice_model->cnt;
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}
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/* Call the dff subckt*/
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fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt);
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/* print ports*/
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fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
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/* Local vdd and gnd, spice_model name,
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* Global vdd for hardlogic to split
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*/
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fprintf(fp, "gvdd_%s[%d] sgnd %s\n", spice_model->prefix, spice_model->cnt, spice_model->name);
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/* End */
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fprintf(fp, ".eom\n");
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spice_model->cnt++;
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/*Free*/
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free(formatted_subckt_prefix);
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free(port_prefix);
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return;
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}
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void fprint_pb_primitive_io(FILE* fp,
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char* subckt_prefix,
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t_logical_block* mapped_logical_block,
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t_pb_graph_node* prim_pb_graph_node,
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int index,
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t_spice_model* spice_model) {
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int num_pad_port = 0; /* INOUT port */
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t_spice_model_port** pad_ports = NULL;
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int num_input_port = 0;
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t_spice_model_port** input_ports = NULL;
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int num_output_port = 0;
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t_spice_model_port** output_ports = NULL;
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int num_clock_port = 0;
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t_spice_model_port** clock_ports = NULL;
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int num_sram_port = 0;
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t_spice_model_port** sram_ports = NULL;
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int i;
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int num_sram = 0;
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int expected_num_sram = 0;
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int* sram_bits = NULL;
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int cur_num_sram = 0;
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char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/
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t_pb_type* prim_pb_type = NULL;
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char* port_prefix = NULL;
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char* sram_vdd_port_name = NULL;
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/* Ensure a valid file handler*/
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if (NULL == fp) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Ensure a valid pb_graph_node */
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if (NULL == prim_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_graph_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find ports*/
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pad_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INOUT, &num_pad_port, TRUE);
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input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
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output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
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clock_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_port, TRUE);
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sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
|
||
|
|
|
||
|
|
/* Asserts */
|
||
|
|
assert(SPICE_MODEL_IOPAD == spice_model->type);
|
||
|
|
|
||
|
|
/* Initialize */
|
||
|
|
|
||
|
|
prim_pb_type = prim_pb_graph_node->pb_type;
|
||
|
|
|
||
|
|
if (NULL != mapped_logical_block) {
|
||
|
|
fprintf(fp, "***** Logical block mapped to this IO: %s *****\n",
|
||
|
|
mapped_logical_block->name);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Generate Subckt for pb_type*/
|
||
|
|
/*
|
||
|
|
port_prefix = (char*)my_malloc(sizeof(char)*
|
||
|
|
(strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1
|
||
|
|
+ strlen(my_itoa(index)) + 1 + 1));
|
||
|
|
sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index);
|
||
|
|
*/
|
||
|
|
/* Simplify the port prefix, make SPICE netlist readable */
|
||
|
|
port_prefix = (char*)my_malloc(sizeof(char)*
|
||
|
|
(strlen(prim_pb_type->name) + 1
|
||
|
|
+ strlen(my_itoa(index)) + 1 + 1));
|
||
|
|
sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index);
|
||
|
|
|
||
|
|
/* Decode SRAM bits */
|
||
|
|
assert((1 == num_sram_port)&&(NULL != sram_ports)&&(1 == sram_ports[0]->size));
|
||
|
|
num_sram = count_num_sram_bits_one_spice_model(spice_model, -1);
|
||
|
|
/* what is the SRAM bit of a mode? */
|
||
|
|
/* If logical block is not NULL, we need to decode the sram bit */
|
||
|
|
if (NULL != mapped_logical_block) {
|
||
|
|
assert(NULL != mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits);
|
||
|
|
sram_bits = decode_mode_bits(mapped_logical_block->pb->pb_graph_node->pb_type->mode_bits, &expected_num_sram);
|
||
|
|
assert(expected_num_sram == num_sram);
|
||
|
|
} else {
|
||
|
|
/* Initialize */
|
||
|
|
sram_bits = (int*)my_calloc(num_sram, sizeof(int));
|
||
|
|
for (i = 0; i < num_sram; i++) {
|
||
|
|
sram_bits[i] = sram_ports[0]->default_val;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get current counter of mem_bits, bl and wl */
|
||
|
|
cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info);
|
||
|
|
|
||
|
|
/* Definition line */
|
||
|
|
fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix);
|
||
|
|
/* print ports*/
|
||
|
|
fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
|
||
|
|
/* Local vdd and gnd*/
|
||
|
|
fprintf(fp, "svdd sgnd\n");
|
||
|
|
/* Definition ends*/
|
||
|
|
|
||
|
|
/* Call the iopad subckt*/
|
||
|
|
fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt);
|
||
|
|
/* Only dump the global ports belonging to a spice_model
|
||
|
|
* Do not go recursive, we can freely define global ports anywhere in SPICE netlist
|
||
|
|
*/
|
||
|
|
if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) {
|
||
|
|
fprintf(fp, "+ ");
|
||
|
|
}
|
||
|
|
/* print regular ports*/
|
||
|
|
fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type);
|
||
|
|
/* Print inout port */
|
||
|
|
fprintf(fp, " %s%s[%d] ",
|
||
|
|
gio_inout_prefix,
|
||
|
|
spice_model->prefix,
|
||
|
|
spice_model->cnt);
|
||
|
|
/* Print SRAM ports */
|
||
|
|
for (i = 0; i < num_sram; i++) {
|
||
|
|
fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]);
|
||
|
|
/* We need the invertered signal for better convergency */
|
||
|
|
fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, 1 - sram_bits[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Local vdd and gnd, spice_model name,
|
||
|
|
* TODO: Global vdd for i/o pad to split?
|
||
|
|
*/
|
||
|
|
fprintf(fp, "%s_%s[%d] sgnd %s\n",
|
||
|
|
spice_tb_global_vdd_port_name,
|
||
|
|
spice_model->prefix,
|
||
|
|
spice_model->cnt,
|
||
|
|
spice_model->name);
|
||
|
|
|
||
|
|
/* Print the encoding in SPICE netlist for debugging */
|
||
|
|
fprintf(fp, "***** SRAM bits for IOPAD[%d] *****\n",
|
||
|
|
spice_model->cnt);
|
||
|
|
fprintf(fp, "*****");
|
||
|
|
for (i = 0; i < num_sram; i++) {
|
||
|
|
fprintf(fp, "%d", sram_bits[i]);
|
||
|
|
}
|
||
|
|
fprintf(fp, "*****\n");
|
||
|
|
|
||
|
|
/* Call SRAM subckts*/
|
||
|
|
/* Give the VDD port name for SRAMs */
|
||
|
|
sram_vdd_port_name = (char*)my_malloc(sizeof(char)*
|
||
|
|
(strlen(spice_tb_global_vdd_io_sram_port_name)
|
||
|
|
+ 1 ));
|
||
|
|
sprintf(sram_vdd_port_name, "%s",
|
||
|
|
spice_tb_global_vdd_io_sram_port_name);
|
||
|
|
/* Now Print SRAMs one by one */
|
||
|
|
for (i = 0; i < num_sram; i++) {
|
||
|
|
fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Store the configuraion bit to linked-list */
|
||
|
|
add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram,
|
||
|
|
num_sram, sram_bits);
|
||
|
|
|
||
|
|
/* End */
|
||
|
|
fprintf(fp, ".eom\n");
|
||
|
|
|
||
|
|
/* Back-annotate to logical block */
|
||
|
|
if (NULL != mapped_logical_block) {
|
||
|
|
mapped_logical_block->mapped_spice_model = spice_model;
|
||
|
|
mapped_logical_block->mapped_spice_model_index = spice_model->cnt;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the spice_model counter */
|
||
|
|
spice_model->cnt++;
|
||
|
|
|
||
|
|
/*Free*/
|
||
|
|
my_free(formatted_subckt_prefix);
|
||
|
|
my_free(port_prefix);
|
||
|
|
my_free(sram_vdd_port_name);
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
|