OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.act

clk 0.500000 2.000000
a 0.502000 0.197200
b 0.485400 0.202800
c 0.248000 0.176800
a_reg 0.502000 0.197200
b_reg 0.485400 0.202800
n10 0.248000 0.043259
n13 0.502000 0.098994
n17 0.485400 0.098439
[Benchmark] Add a micro benchmark to test pipelined architecture 2021-01-10 11:21:30 -06:00			`clk 0.500000 2.000000`
[Benchmark] Bug fix in pipelined and2 benchmark 2021-01-10 11:27:59 -06:00			`a 0.502000 0.197200`
			`b 0.485400 0.202800`
			`c 0.248000 0.176800`
			`a_reg 0.502000 0.197200`
			`b_reg 0.485400 0.202800`
			`n10 0.248000 0.043259`
			`n13 0.502000 0.098994`
			`n17 0.485400 0.098439`