OpenFPGA/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v

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module counter(clk, q, rst);
input clk;
input rst;
output [7:0] q;
reg [7:0] q;
always @ (posedge clk)
begin
if(rst)
q <= 8'b00000000;
else
q <= q + 1;
end
endmodule