74 lines
5.2 KiB
Markdown
74 lines
5.2 KiB
Markdown
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# OpenFPGA flow options
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Usage -> **fpga_flow *-options <value>* **<br />
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Mandatory options: <br />
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- -conf <file> : *specify the basic configuration files for fpga_flow*
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- -benchmark <file> : *the configuration file contains benchmark file names*
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- -rpt <file> : *CSV file consists of data*
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- -N <int> : *N-LUT/Matrix*
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Other Options:<br />
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## General
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- -matlab_rpt <data_name> : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script*
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- -I <int> : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen*
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- -K <int> : *K-LUT, mandatory when standard flow is chosen*
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- -M <int> : *M-Matrix, mandatory when mpack1 flow is chosen*
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- -power : *run power estimation oriented flow*
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- -black_box_ace: *run activity estimation with black box support. It increase the power.*
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- -remove_designs: *remove all the old results.*
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- -multi_thread <int>: *turn on the mutli-thread mode, specify the number of threads*
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- -multi_task <int>: *turn on the mutli-task mode*
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- -parse_results_only : *only parse the flow results and write CSV report.*
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- -debug : *debug mode*
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- -help : *print usage*
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## ODIN II
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- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
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- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
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- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow *
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## ABC
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- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.*
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- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.*
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## ACE
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- -ace_p <float> : *specify the default signal probablity of PIs in ACE2.*
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- -ace_d <float> : *specify the default signal density of PIs in ACE2.*
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## VPR - Original Version
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- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.*
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- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.*
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- -vpr_max_router_iteration <int> : *specify the max router iteration in VPR.*
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- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.*
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- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.*
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- -min_route_chan_width <float> : *turn on routing with <float>* min_route_chan_width.*
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- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.*
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## VPR - FPGA-X2P Extension
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- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE*
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- -vpr_fpga_x2p_signal_density_weight <float>: *specify the option signal_density_weight of VPR FPGA SPICE*
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- -vpr_fpga_x2p_sim_window_size <float>: *specify the option sim_window_size of VPR FPGA SPICE*
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- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization*
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## VPR - FPGA-SPICE Extension
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- -vpr_fpga_spice <task_file> : *turn on SPICE netlists print-out in VPR, specify a task file*
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- -vpr_fpga_spice_sim_mt_num <int>: *specify the option sim_mt_num of VPR FPGA SPICE*
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- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE*
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- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE*
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- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE*
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- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE*
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- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE*
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- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
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- -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
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## VPR - FPGA-Verilog Extension
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- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
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- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
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- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files*
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- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files*
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- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator*
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- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping*
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- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation*
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- -vpr_fpga_verilog_report_timing_rpt_path <path_to_generate_reports> : *Specify path for report timing*
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- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R*
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- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA*
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- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE*
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- -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
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## VPR - FPGA-Bitstream Extension
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- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*
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