OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/aib.v

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//-----------------------------------------------------
// Design Name : AIB interface
// File Name : aib.v
// Function : A wrapper for AIB interface
// Coder : Xifan Tang
//-----------------------------------------------------
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module AIB (
input TX_CLK,
input RX_CLK,
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inout[0:79] PAD,
input[0:79] TX_DATA,
output[0:79] RX_DATA);
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// May add the logic function of a real AIB
// Refer to the offical AIB github
// https://github.com/intel/aib-phy-hardware
endmodule