OpenFPGA/openfpga_flow/misc/qlf_yosys.ys

# Yosys synthesis script for ${TOP_MODULE}

plugin -i ql-qlf

# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}

synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}

write_verilog -noattr -nohex ${OUTPUT_VERILOG}
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00			`# Yosys synthesis script for ${TOP_MODULE}`
add plugins, set yosys install for plugin 2021-11-03 20:52:09 -05:00
			`plugin -i ql-qlf`

Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00			`# Read verilog files`
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 02:21:29 -06:00			`read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}`
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00
Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 03:46:06 -06:00			`synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}`
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00
[Script] Update quicklogic's script to output correct verilog file name 2021-03-08 22:39:44 -06:00			`write_verilog -noattr -nohex ${OUTPUT_VERILOG}`