OpenFPGA/openfpga_flow/misc/qlf_yosys.ys

# Yosys synthesis script for ${TOP_MODULE}

plugin -i ql-qlf

# Read verilog files
${READ_VERILOG_FILE}

synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}

write_verilog -noattr -nohex ${OUTPUT_VERILOG}
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00			`# Yosys synthesis script for ${TOP_MODULE}`
add plugins, set yosys install for plugin 2021-11-03 20:52:09 -05:00
			`plugin -i ql-qlf`

Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00			`# Read verilog files`
			`${READ_VERILOG_FILE}`

Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-08 00:01:35 -06:00			`synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}`
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00
[Script] Update quicklogic's script to output correct verilog file name 2021-03-08 22:39:44 -06:00			`write_verilog -noattr -nohex ${OUTPUT_VERILOG}`