2018-09-13 16:38:41 -05:00
|
|
|
.. OpenFPGA documentation master file, created by
|
|
|
|
|
sphinx-quickstart on Thu Sep 13 12:15:14 2018.
|
|
|
|
|
You can adapt this file completely to your liking, but it should at least
|
|
|
|
|
contain the root `toctree` directive.
|
|
|
|
|
|
|
|
|
|
Welcome to OpenFPGA's documentation!
|
|
|
|
|
====================================
|
|
|
|
|
|
2018-09-13 18:39:57 -05:00
|
|
|
For more information on the ABC see .
|
|
|
|
|
For more information on the VPR see
|
|
|
|
|
For more information on the original FPGA architecture description language see
|
2018-09-13 16:38:41 -05:00
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:maxdepth: 2
|
|
|
|
|
:caption: Extended Architecture Description Language
|
|
|
|
|
|
2018-09-13 18:39:57 -05:00
|
|
|
arch_lang/index
|
2018-09-13 16:38:41 -05:00
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:maxdepth: 2
|
|
|
|
|
:caption: OpenFPGA VPR Usage
|
2018-09-13 18:39:57 -05:00
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:caption: FPGA-SPICE: SPICE Auto-Generation
|
|
|
|
|
|
|
|
|
|
fpga_spice/index
|
|
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:caption: FPGA-Verilog: Verilog Auto-Generation
|
|
|
|
|
|
|
|
|
|
fpga_verilog/index
|
|
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:caption: FPGA-Bitstream: Bitstream Generator
|
|
|
|
|
|
|
|
|
|
fpga_bitstream/index
|
2018-09-13 16:38:41 -05:00
|
|
|
|
|
|
|
|
.. toctree::
|
|
|
|
|
:maxdepth: 2
|
|
|
|
|
:caption: Tutorial
|
2018-09-13 18:39:57 -05:00
|
|
|
|
|
|
|
|
tutorials/index
|
2018-09-13 16:38:41 -05:00
|
|
|
|
|
|
|
|
.. toctree::
|
2018-09-13 18:39:57 -05:00
|
|
|
:maxdepth: 2
|
2018-09-13 16:38:41 -05:00
|
|
|
:caption: Appendix
|
|
|
|
|
|
|
|
|
|
contact
|
2018-09-13 18:39:57 -05:00
|
|
|
reference
|
2018-09-13 16:38:41 -05:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Indices and tables
|
|
|
|
|
==================
|
|
|
|
|
|
|
|
|
|
* :ref:`genindex`
|
|
|
|
|
* :ref:`modindex`
|
|
|
|
|
* :ref:`search`
|
