9 lines
217 B
Plaintext
9 lines
217 B
Plaintext
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read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} }
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set_top r:${SOURCE_TOP_DIR}
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read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} }
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set_top i:${IMPL_TOP_DIR}
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match
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${MATCH_MODUEL_LIST}
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verify
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