coriolis/crlcore/etc/common
Jean-Paul Chaput e711ce8dd2 More configuration parameters for P&R Conductor, for experimenting.
* Change: In Hurricane::Viewer::ExceptionWidget & CRL/python/helpers/io.py,
    downscale icons for non-HiDPI screen.
* Change: In CRL/etc/common/display.py, change the display threshold of
    METAL1 layer so it do not appear at high scaling.
* New: In Etesian, activate the "setFixedAbHeight()" feature and export it
    to Python. Allows to increase the space margin at constant height.
      To be used by the P&R conductor.
* Change: In Unicorn/cgt.py, when running a script, insert the current
    working directory at head of the sys.path, not at the end. So installed
    modules do not shadow local one.
* New: In Anabatic::Edge, new accessor "getRawcapacity()" to know the full
    capacity of the edge, that is, the real maximum number of tracks that
    can go through the associated side.
* Change: In Katana/BloatProfile/Slice::tagsOverloaded(), bloating policy
    change, now bloat all the instances under the GCell, not only the first
    one.
* Change: In KatanaEngine::runGlobalRouter(), restore the search halo growth
    policy to expanding of 3 GCells every 3 iterations.
      New metrics displayed, the edge wire length length overload.
* Change: In cumulus/plugins/ConductorPlugin.py, now accepts the following
    configuration parameters:
      - "anabatic.globalIterationsEstimate", maximum number of global
        iterations during the bloating computation passes.
      - "conductor.useFixedAbHeight", tells wether the additionnal blank
        space must be added so the aspect ratio is kept or the height is
	kept (and the block become wider).
    Disable the display of "rubber" to unclutter a little the view.
2019-12-15 19:28:54 +01:00
..
__init__.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
analog.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
analog.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
colors.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
devices.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
devices.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
display.conf Correct CellWidget & CellPrinter to be really WYSIWYG. 2019-02-20 18:24:43 +01:00
display.py More configuration parameters for P&R Conductor, for experimenting. 2019-12-15 19:28:54 +01:00
etesian.conf Added core2chip support for Phenitec80. 2019-09-17 17:05:54 +02:00
etesian.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
hMetis.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
kite.conf Enable the display of GCells as a density map (and not boundaries). 2016-09-10 18:49:48 +02:00
kite.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
mauka.conf Buffer cell configuration in ClockTree. More config parameters in Chip. 2014-09-02 11:17:47 +02:00
misc.conf In CRL, update real conf. files. Smarter management of pin in LEF parser. 2018-01-06 16:18:33 +01:00
misc.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
nimbus.conf Bug in Python proxy deallocation. Update to latest Coloquinte. 2015-02-13 23:38:55 +01:00
patterns.conf Added METCAP layer, for MIM capacitors. 2016-03-06 12:40:23 +01:00
patterns.py First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
stratus1.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
stratus1.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
technology.conf Upgrade of Katana detailed router to support Arlet 6502. 2019-07-28 23:20:00 +02:00
technology.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00