b48f9b40b8
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
1. Bad condition for the use of VstUseConcat. Must be used *only*
when there is more than *one* mapped name.
2. Missing case, when there is exactly *one* mapped name, that
means that we have one full width vector to vector assignement.
There may be another weakness here, for the portmap we assumes
that both vector are mapped in the *same* direction (which is
"downto" by our convention).
3. In the "bit by bit mapping case" (every bits of the vector are
differents bits), use the "signal + bit index" name instead of
juste the signal name (i.e. full width).
Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
we can avoid the YOSYS_FLATTEN.
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| LibraryManager | ||
| ccore | ||
| cyclop | ||
| fonts | ||
| pyCRL | ||
| x2y | ||
| CMakeLists.txt | ||