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The VST driver may suppress linkage type. 

* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
    undefined directions are typed "linkage". This may not be compatible
    with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
   the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
    of the "linkage" type.
This commit is contained in:
Jean-Paul Chaput 2020-06-24 23:27:21 +02:00
parent 1ccb9c340f
commit b23f620c5d
6 changed files with 16 additions and 5 deletions
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8
crlcore/src/ccore/alliance/vst/VhdlEntity.cpp
View File

@ -281,7 +281,9 @@ namespace Vhdl {
for ( auto isignal=internalSignals.begin(); isignal!=internalSignals.end() ; ++isignal ) {
out << tab;
(*isignal)->toVhdlPort( out, width, Entity::AsInnerSignal|(_flags & Entity::IeeeMode) );
(*isignal)->toVhdlPort( out, width, Entity::AsInnerSignal
|(_flags & Entity::IeeeMode)
|(_flags & Entity::VstNoLinkage) );
out << ";\n";
}
out << "\n";
@ -305,7 +307,9 @@ namespace Vhdl {
size_t ioCount = 0;
for ( auto isignal=ioSignals.begin(); isignal!=ioSignals.end() ; ++isignal ) {
if (ioCount) out << "\n" << tab << " ; ";
(*isignal)->toVhdlPort( out, width, Entity::AsPortSignal|(_flags & Entity::IeeeMode ) );
(*isignal)->toVhdlPort( out, width, Entity::AsPortSignal
|(_flags & Entity::IeeeMode)
|(_flags & Entity::VstNoLinkage ) );
++ioCount;
}
out << "\n" << tab << " );";

5
crlcore/src/ccore/alliance/vst/VhdlSignal.cpp
View File

@ -33,6 +33,7 @@ namespace Vhdl {
: _name(name)
{ }
Signal::~Signal ()
{ }
@ -54,7 +55,9 @@ namespace Vhdl {
case Net::Direction::IN: out << "in"; break;
case Net::Direction::OUT: out << "out"; break;
case Net::Direction::INOUT: out << "inout"; break;
default: out << "linkage";
default:
if (flags & Entity::VstNoLinkage) out << "in";
else out << "linkage";
}
}

1
crlcore/src/ccore/alliance/vst/VstDriver.cpp
View File

@ -42,6 +42,7 @@ namespace CRL {
unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
if (saveState & Catalog::State::VstNoLowerCase) entityFlags |= Vhdl::Entity::VstNoLowerCase;
if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage;
//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );

1
crlcore/src/ccore/crlcore/Catalog.h
View File

@ -88,6 +88,7 @@ namespace CRL {
, Foreign = 1 << 8
, VstUseConcat = 1 << 9
, VstNoLowerCase = 1 << 10
, VstNoLinkage = 1 << 11
, Views = Physical|Logical
};
// Constructors.

5
crlcore/src/ccore/crlcore/VhdlEntity.h
View File

@ -66,9 +66,10 @@ namespace Vhdl {
, AsInnerSignal = 0x0010
, VstUseConcat = 0x0020
, VstNoLowerCase = 0x0040
, OptionMask = VstUseConcat|VstNoLowerCase
, VstNoLinkage = 0x0080
, OptionMask = VstUseConcat|VstNoLowerCase|VstNoLinkage
};
const unsigned int ModeMask = VstUseConcat|VstNoLowerCase;
const unsigned int ModeMask = VstUseConcat|VstNoLowerCase|VstNoLinkage;
public:
static std::vector<Entity*>&
getAllEntities ();

1
crlcore/src/pyCRL/PyCatalogState.cpp
View File

@ -147,6 +147,7 @@ extern "C" {
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLinkage ,"VstNoLinkage");
LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views");
}