coriolis/crlcore
Jean-Paul Chaput d670de4125 Added support for 3 metal layers symbolic Phenitec 0.6um.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
    layout targeted for Phenitec 0.6um (do not contains any NDA
    covered informations). Could be used for any 3 metal layers
    techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
    disable stack error when there is no slave component on the stack
    (happens when the stack consists only of one contact).
2019-08-12 15:41:17 +02:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Full update of the generated documentation for version 2.3 2019-05-27 18:49:51 +02:00
etc Added support for 3 metal layers symbolic Phenitec 0.6um. 2019-08-12 15:41:17 +02:00
python In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
src Remove VHDL driver extension/property after use. 2019-08-08 14:12:22 +02:00
CMakeLists.txt Add a fully generated documentation in the git repository. 2018-06-06 18:42:26 +02:00