coriolis/crlcore
Jean-Paul Chaput 5914e16f26 Added management for "phlib" I/O pad external connectors (for cougar/lvx).
* New: In CRL::ApDriver::DumpSegments(), drive as top-level segments the
    RoutingPads using a Pin, and not only using a segment. They are not
    exported as top level Pin but only as Segment as they do belong to
    a deeper level.
* New: In Cumulus/plugins/PadsCorona.Side._placePads(), now manage both
    "pxlib" and "phlib*". Pad library management is still hardcoded, this
    should be made a configuration option someday.
2019-10-05 16:04:12 +02:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Full update of the generated documentation for version 2.3 2019-05-27 18:49:51 +02:00
etc Adjusted routing pitch for METAL4 to METAL7 for FreePDK45 symbolic. 2019-09-19 23:52:03 +02:00
python In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
src Added management for "phlib" I/O pad external connectors (for cougar/lvx). 2019-10-05 16:04:12 +02:00
CMakeLists.txt Add a fully generated documentation in the git repository. 2018-06-06 18:42:26 +02:00