coriolis/crlcore
Jean-Paul Chaput 5877691cde The VST driver can now be setup to use or not concat ('&') in PORT MAP.
* New: In CRL::AllianceFramework::saveCell(), through the view flag we
    can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the
    driver tu use or not the concat '&' in PORT MAP statements.
      It is not completely clean that the flag for controlling the VST
    driver behavior is put in the Catalog states, but it's easier for
    now...
      And, of course, exported at Python level.
2019-08-13 14:46:23 +02:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Full update of the generated documentation for version 2.3 2019-05-27 18:49:51 +02:00
etc Added support for 3 metal layers symbolic Phenitec 0.6um. 2019-08-12 15:41:17 +02:00
python In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
src The VST driver can now be setup to use or not concat ('&') in PORT MAP. 2019-08-13 14:46:23 +02:00
CMakeLists.txt Add a fully generated documentation in the git repository. 2018-06-06 18:42:26 +02:00