Nets

Synopsys

netInput = LogicIn ( name, arity )

Description

Instanciation of net. Differents kind of nets are listed below :

• LogicIn : Creation of an input port
• LogicOut : Creation of an output port
• LogicInOut : Creation of an inout port
• LogicUnknown : Creation of an input/output port which direction is not defined
• TriState : Creation of a tristate port
• CkIn : Creation of a clock port
• VddIn : Creation of the vdd alimentation
• VssIn : Creation of the vss alimentation
• Signal : Creation of an internal net

Parameters

• name : Name of the net (mandatory argument)
• arity : Arity of the net (mandatory argument)
• indice : For buses only : the LSB bit (optional argument : set to 0 by default)
  

Only CkIn, VddIn and VssIn do not have the same parameters : there is only the name parameter (they are 1 bit nets).

Attributes

• _name : Name of the net
• _arity : Arity of the net (by default set to 0)
• _ind : LSB of the net
• _ext : Tells if the net is external or not (True/False)
• _direct : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN")
• _h_type : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK")
• _type : The arithmetic type of the net ( "nr" )
• _st_cell : The stratus cell which the net is instanciated in
• _real_net : If the net is a part of a net (Sig) it is the real net corresponding
• _alias : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net
• _to_merge : [] by default. The same as _alias
• _to_cat : [] by default. The same as _alias
  

And, in connection with Hurricane :

• _hur_net : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : net._hur_net[0] ).

Methods

• Buffer : Instanciation of a Buffer
• Shift : Instanciation of a shifter
• Mux : Instanciation of a multiplexor
• Reg : Instanciation of a register
• Eq/Ne : Instanciation of comparison generator
• Extend : A net is extended
• Alias : A net is an alias of another net
• Delete : Deletion of the Hurricane nets
  

And the overloards :

• __init__ : Initialisation of nets
• __le__ : initialisation of a net thanks to <= notation
• __getitem__, __geslice__ : Creation of "Sig" nets : which are part of nets (use of [] and [:])
• __and__, __or__, __xor__, __invert__ : boolean operation with &, |, , 
• __add__, __mul__, __div__ : arithmetic operators with +, * and /