Commit Graph

3 Commits

Author SHA1 Message Date
Jean-Paul Chaput db60fe0aa6 New coriolis launcher. Configuration files cleanup.
* Change: In CRL Core, simplify the loading sequence. The technology,
    both symbolic and real is now loaded directly from coriolisInit.py
    and not through the Alliance loader. This was a leftover from the
    time configuration was in XML. Remove others traces of XML loading.
      Remove SYMB_TECHNO_NAME, REAL_TECHNO_NAME & DISPLAY from the Alliance
    environement, as they was no longer used.
      Note that technology *still* need to be loader *after* Alliance
    framework has been initialized.
      Gauge information is moved from <alliance.conf> to <kite.conf>.
* Bug: In Coloquinte, in optimization_subproblems.cxx static variables
    must not be inlined. Generate a problem when linking in debug mode
    (seems the symbol gets optimised out).
* Bug: In Katabatic, in Grid::getGCell(), when the coordinate is *outside*
    the area, do not try to find a GCell, directly return NULL.
* New: In Unicorn, create a generic command launcher named "coriolis" which
    automatically take cares of all environement setup, then run a command
    by default, it's <cgt>, but it can be anything. For example: <zsh>.
2015-04-13 18:54:09 +02:00
Jean-Paul Chaput 8566126acc Adding Configuration support to Etesian.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
    "importeds", it will be the home of all the externally
    devellopped softwares that are needed to build Coriolis.
      Add explicit support for Fedora ("Linux.fc") and uses
    site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
    own configuration variables instead of borrowing those of
    Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
    as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
    to match the new Etesian/Python interface.
2015-02-27 18:16:03 +01:00
Jean-Paul Chaput a3963716b1 Correction in plugins to support msxlib compatible pads.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
    variable to define the pad model name extension ("px" for "sxlib
    and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
    of used for power & clock supply. We may remove the extention in
    the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
    longer place the accessing contact *at the center* of the
    RoutingPad. It works under sxlib because buffers & registers all
    have same size terminals. But this is not true under vsxlib,
    leading to misaligned contacts & wires. Now systematically place
    on the slice midlle track (maybe with one pitch above or below).
      This is still very weak as we do not check if the terminal
    reach were the contact is being put. Has to be strenthened in
    the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
    clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
    of PyInt for DbU conversions. In PyHurricane argument converter,
    automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
    in case of discrepency in global net connections (i.e. no net
    of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
    model name to find "pck_" or "pvddeck_", do not compare the
    extension part. But we still use hard-coded stem pad names,
    maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
    was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
    RoutingPads of fixed nets, they are already through the
    BuildPowerRails stage (and it's causing scary overlap warning
    messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
    deep-plug when the core is flat (not sub-modules). All the new
    nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
    that the core is aligned on the GCell grid (i.e. the slice
    grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
    while looking for the bigger N-E RoutingPad. Forgot to decrement
    the index...
2014-09-13 17:45:30 +02:00